Hi, this kind of structure don't work above 100kHz !! and i have 4Mhz input signal !
The first stage is an high speed Amp Op, and i just want to have more current at the output. So, I think a can use a simple MOSFET Push Pull at the ouput Amp Op and a negative feedback at the input of the Amp Op to disable the distorsion !! But i don't know how design this Push Pull !!
Do you need this for a on-chip design or you use descrete components?
Here's what I think could be done for a on-chip design. You have the output of your op-amp. Take it and pass it through:
1) a NMOS source follower - to level-shift it downwards;
2) a PMOS sourse follower - to level shift it upwards;
After the sourse followers you have your push-pull MOST stage with NMOST on the top and PMOST at the bottom. Connect the NMOST gate to the output of the PMOS source follower and the PMOST gate to the output of the NMOS source follower. This should work but probably needs some adjustment to match the gate-source voltages. I am not sure though if you have to put a feed-back around the whole thing or only around the opamp. If you put it aroun the whole schematic you should pay particular attention to stability issues. From this configuration you don't expect to get higher open-loop gain but you for sure introduce more poles and because your opamp is high-speed you may come to non-dominant poles which are close or even before the unity-gain frequency.