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How can I deal with 3rd HD in a 2nd SigmaDelta Modulator,plz

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DZC

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I am designing a second order sigma_delta modulator for audio application.
The input frequency is 8kHz and the sampling rate is 1MHz.
The design target is 16bit but he simulated 3rd distortion of the SDM is as high as -54dB.
The slew rate of the first OTA designed to be 20V/µs.

What might is reason of the distortion and how can I get rid of them?
Thanks for all your suggestion.
 

jiangxb

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Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator

hi DZC,

firstly, maybe the slew rate is too small, so increase it and try again.
do you use multibit quantizer?
from your psd the resolution of 16 bits is difficult to achieve.
 

PoojanWagh

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Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator

It’s possible that the OTA is limiting you. Doing a matlab model of the sigma-delta and running it should tell you whether it is a circuit problem or a system-level problem. My hunch is that it’s a system-level problem: the noise-shaping filter doesn’t have enough gain at 24 kHz to suppress the 3rd order distortion.

Seems like the sigma-delta loop doesn’t have a lot of gain where you want it. I would suggest putting in some noise-transfer zeros (noise-shaping filter poles). This would move the nulls off dc and closer to where you want them. You may need to go to a 3rd-order sigma-delta to do this (one NTF zero at dc and two complex ones at 24 kHz or so).

The other alternative, as stated before, is to improve the linearity of the quantizer: go to a multibit.

--
Poojan

https://www.circuitdesign.info/2008...al-with-3rd-hd-in-a-2nd-sigmadelta-modulator/
 

    DZC

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hannerfherder

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Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator

Hi all:

A multibit quantizer will improve SNR, but if it is not perfectly linear, it can degrade distortion. A two level quantizer (i.e. a comparator) is inherently linear, and will not introduce distortion.

In a 2nd order modulator, the distortion of the 2nd integrator is shaped to 1st order, so it is probably not the limiting factor. The issue is in the first integrator. It could be op amp limitations: you will see that in simple settling tests. It could be in gain range issues: does the amp have gain at the output voltages you need it to swing to? Is it modulator overload? (i.e. how big is your reference compared to your input signal?) It could even be poor linearity in your sampling network. (take your sampling capacitor and switch network, turn the sample switches on the whole simulation, run a max input sinewave in and and look at the result voltage across the sampling caps: is it linear?)

I hope this helps.
 

PoojanWagh

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Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator

hannerfherder:

I wouldn't say that a 1-bit quantizer is inherently linear. I'd say that a 1-bit DAC is inherently linear. (And even that's tricky.) For example, if I put a sinusoid into a 1-bit quantizer, I am going to see <del>distortion</del>--well, harmonics, anyway.
 

hannerfherder

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Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator

Hi PoojanWagh

I am not the best to explain these things. The best I've seen is Brian Paul Brandt's thesis "Oversampled Analog-to-Digital Conversion", available from Stanford Integrated Circuits Lab as Technical Report ICL91-009.

I see what you mean, if the quantizer is not in the SD feedback loop.

But when the comparactor (1 bit quantizer) is embedded in the loop, the harmonics you refer to are, in fact, the quantization noise, and the feedback of the loop will force it to be shaped out of band (most of it, anyway). That is the whole point of sigma delta modulation.

If you use a multilevel quantizer and have nonlinearity, it will show up as distortion. And all kind of randomization techniques are used to try to shape that nonlinearity out of band as well.

Is this distortion issue in simulation or real silicon? If we are talking simulation, everything will match perfectly anyway and a multilevel quantizer will improve the SNR.

Thanks for your thoughtful reply. I need to qualify what I am saying better in the future.

Best Regards,
Hannerfherder
 

PoojanWagh

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Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator

hannerfherder said:
But when the comparactor (1 bit quantizer) is embedded in the loop, the harmonics you refer to are, in fact, the quantization noise, and the feedback of the loop will force it to be shaped out of band (most of it, anyway). That is the whole point of sigma delta modulation.
Agreed. That's my point. The figure that the OP posted indicates to me that (s)he doesn't have enough gain in the loop at 24 kHz. You can see the quantization noise rising well before 24 kHz. If (s)he wants things clean out to 24 kHz, (s)he needs more bandwidth. Thus the prescription for a non-dc noise-transfer zero.
hannerfherder said:
If you use a multilevel quantizer and have nonlinearity, it will show up as distortion. And all kind of randomization techniques are used to try to shape that nonlinearity out of band as well.

Is this distortion issue in simulation or real silicon? If we are talking simulation, everything will match perfectly anyway and a multilevel quantizer will improve the SNR.
Agreed. Improving quantizer linearity will definitely help, both in real silicon and in simulation. In real silicon, the performance won't be as good as in simulation--but it will likely be better than a single-bit quantizer.

hannerfherder said:
Thanks for your thoughtful reply. I need to qualify what I am saying better in the future.

You're doing great. After all, the point of discussion (IMHO) is to point out differences. The characteristic of great discussion is that the differences are reduced in some way. I thoroughly enjoyed this discussion.

--
Poojan
https://www.circuitdesign.info
 

skythunder

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Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator

If you used a latched comparator as the 1-bit quantizer, I do suggest you add a pre-amplifier before the comparator. It will improve the non-linear gain of the quantizer, which may be the firsr cause of the third harmonic.
 

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