Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How can i balance the clock latency in different gated clock

Status
Not open for further replies.

Nobody

Full Member level 3
Joined
Oct 4, 2001
Messages
165
Helped
9
Reputation
16
Reaction score
7
Trophy points
1,298
Location
Formosa
Activity points
1,593
How can i make the constraint(in Synopsys and
apollo) to push the different gated clocks domain into balanced clock's latency ?
 

cdic

Advanced Member level 4
Joined
Jun 28, 2001
Messages
103
Helped
5
Reputation
10
Reaction score
3
Trophy points
1,298
Location
silly valley
Activity points
882
Clocks and Reset signals are dealed with in back-end, only in the back-end, you really know how to balance it, what a insertion delay for clocks is reasonable.
 
  • Like
Reactions: ivlsi

    ivlsi

    points: 2
    Helpful Answer Positive Rating

msdnge

Junior Member level 2
Joined
Dec 12, 2001
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
108
Firstly, after synthesized in Synopsys, you need to inspect the structure of the gated clock tree. Then in SE or Apollo, you set proper clock tree generation constrants according to the structure. The insertion delay has to be got in several iterations.
Wish you luck
 

hamlock

Newbie level 1
Joined
Feb 21, 2002
Messages
0
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,280
Activity points
30
I need this software too!!

Plz mail me
 

andromeda

Member level 3
Joined
Sep 26, 2002
Messages
65
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Activity points
1,149
Another option is to insert lookup latches for delay insertion between different clock domain flops, when you put them in one scan chain. If latency need to be balanced for some functional reason, we again need delay insertion.
The first option (to force balance clock latency in Clock Tree Synthesis tool) is better, of course.
 

seasonyangd

Member level 3
Joined
Nov 14, 2001
Messages
62
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
China
Activity points
361
when you do synthesis, you can set dont_touch on clock and the reset signal. Then do gated clock synthesis when do p&r use Apollo or other tools. if you do clock between macros, you must define synchoronous ping on the clcok pins. The tools will add some delay cells ( you have defined).
 

rogeret

Member level 4
Joined
Sep 7, 2011
Messages
77
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,864
Another option is to insert lookup latches for delay insertion between different clock domain flops, when you put them in one scan chain. If latency need to be balanced for some functional reason, we again need delay insertion.
The first option (to force balance clock latency in Clock Tree Synthesis tool) is better, of course.
I cant understand this method , could u explain further.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top