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How are timing constraints developed?

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Chaos89

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Hello Techgeeks!

How are Timing constraints developed for a SOC?
and what is meant by tight timing constraints..
 

ThisIsNotSam

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Hello Techgeeks!

How are Timing constraints developed for a SOC?
and what is meant by tight timing constraints..

usually there is some top level budgeting so each block designer knows 'how fast' and 'how big' they can go. it's fairly complicated, as a complex SoC has multi modes, multi VDDs, memories, etc.
 

slutarius

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Hello Techgeeks!

How are Timing constraints developed for a SOC?
and what is meant by tight timing constraints..

Tight constraint is the one that over the actual working condition of a design.
Depends on how much over it is in percentage, you can say it is tight or not.
Eg. clock is 100Mhz, its period is 10ns. Regardless the process margin, you make it 6ns in constraint, so you can called it a tight clock constraint.
 

ThisIsNotSam

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Tight constraint is the one that over the actual working condition of a design.
Depends on how much over it is in percentage, you can say it is tight or not.
Eg. clock is 100Mhz, its period is 10ns. Regardless the process margin, you make it 6ns in constraint, so you can called it a tight clock constraint.

That is not tight, that is impossible. Any clock frequency that is close to the absolute maximum is a tight one.
 

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It could also be considered an over-constrained constraint. In the past for ASIC tools and currently in most FPGA tools. If you over-constrain with a near impossible or impossible constraint the tools would either a) give up and give you whatever the last pass result was (good or bad) or b) spend a ridiculous amount of time then give you something that is significantly slower than using the exact constraint (e.g. ask for 300 MHz need 250MHz but get 200 MHz result).
 

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It could also be considered an over-constrained constraint. In the past for ASIC tools and currently in most FPGA tools. If you over-constrain with a near impossible or impossible constraint the tools would either a) give up and give you whatever the last pass result was (good or bad) or b) spend a ridiculous amount of time then give you something that is significantly slower than using the exact constraint (e.g. ask for 300 MHz need 250MHz but get 200 MHz result).

Exactly. And it gets even more complicated than that. The way most tools are coded today is that they are timing oriented. Once they meet timing, then they go back and apply area and power recovery tricks. If your timing is never met, I believe the results you see for power and area cannot be trusted, maybe they are good enough for some rough estimation.
 

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The question is "what is a tight constraint" not "what is suitable constraint".
Practical situation show many effects of over-constraint, both bad and good, and they are not discussed in this topic.
 

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