there are 2 bjt in a latch up model. PNP and NPN. in the model, the substrates/well are connected to the bases of the BJTs. if there is enough voltage drop in the wells, there is a possibility that these BJTs are triggered because these wells are directly connected to the their bases....if they are triggered, latch up occurs... one way to reduced these voltage drop is to lessen the resistance in the well/substrtate. but how do u do this? just put enough contacts or bias to the wells, and not just near the source.
latch up is generally trigrred when their is a spike( can be noise) at the power supplies happen.
now if you have substrate connections at the source, then the noise pulse will alredy have a low resistive path to ground, thus preventing to develop any potential that can cause latchup.
In CMOS logic a SCR( back to back NPN & PNP structure) is formed and when it triggered ON there is a huge current from VDD to VSS(nearly short ckt). It can be avoided by using substrate contact...because these contacts are n+ (PMOS) or p+(NMOS) these provides a low resistance path towards VDD or VSS reducing the currents flowing in SCR which prevents it from triggering.
if you have a background in layout, we all know that the things you've said are correct but it's better if someone put an illustration for easy understanding. tnx in advance.
The substrate taps are heavily doped (P+ /n+) which means they act as a low resistance path for any leakage current in the substrate thereby inhibiting the formation of voltage required to trigger the parasitic transistors formed, thus avoiding latch up.
I believe this helps.
A fact is that the substrate has some resistivity.Although it is tied to a ground,in its
other position , voltage will be higher than ground because of the current flowing through the substrate.when this voltage exceed the adjacent PN junction ,this junction will foward biased.Now if this PN juction is a pasitic bjt' emitor ,this bjt will
open ,it will added to the propability of latch up occurance.