How a setup and hold margins, or setup & hold values are decided to a flip flop ?
Faced this question in interviews.
it is not decided, it is calculated and very precisely with a lot of simulation. You set the clock waveform and the data input to switch at the same time. It will fail. Then you start moving the data away from the clock in both directions, until it works. There is your hold /setup.
Nobody calculate setup in such way (during characterization of std. cells). The usual approach - moving data close to the clock, and when the output delay start increasing (say in 10 %) it is the setup time.
are you referring to my post?
are you referring to my post?
yes.
Okay, as you are saying, lets say that the data is moving close to clock, and at 1ns before the clock edge, the output goes in meta-stability. This 1ns is the setup time. (Correct me if I am wrong)
Now my question is, how that 1ns margin is set to the flipflop ? Is that decided at the time of flipflop design ? or is that decided based on Master-Slave latch configuration?
Please provide the steps.
Thanks in advance.
Yes. When the setup/hold is large enough, the delay of the flop remains close to the static delay. As setup/hold time reduces, the delay of the cell increases. We accept a delay that remains within 10% of the static delay. The setup/hold point where this occurs is defined as the cell specification.
The method, that you have described, is named pass/fail method. This method is obsoleted now.
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The setup/hold values (measured during cell characterization) are uniq for each cell of your library. These values stored in the timing model (for example in synopsys .lib/.db files), and the static_timing_analysis tool (like primetime) is used these values during chip timing calculation.
If your library flip-flop has setup/hold lesser than you want to apply (you want tight the constraints), you may annotate the cell with your own values - in Synopsys it is command set_annotated_check.
If flip-flop has bigger values, than you should design the new flipflop.
Okay.
Is there any another method for this ?
I mean in digital way.
Suppose for example, I want to design a flipflop using NAND gates, how should I design that flipflop with setup 1ns and hold 0.5ns ? Expecting the answer in digital electronics perspective.
Yes. When the setup/hold is large enough, the delay of the flop remains close to the static delay. As setup/hold time reduces, the delay of the cell increases. We accept a delay that remains within 10% of the static delay. The setup/hold point where this occurs is defined as the cell specification.
The method, that you have described, is named pass/fail method. This method is obsoleted now.
I think everyone is reading into the OPs question incorrectly, which is why the keep asking the same question over and over.
The OP (I believe) wants to know how one would design the library component of a say a DFF that has a specific setup and hold time. This is the transistor level model (the analog circuit) that DFFs are comprised of in a standard cell library. Everyone is too fixated on the 1ns setup, 0.5ns hold, which was only an example if you want to be fixated on something then how about a theoretical future process node...
Say you want your DFF to have this characteristic
25ps setup, 0ps hold
as opposed to this one
22ps setup, 3ps hold
or this one
12.5ps setup, 12.5ps hold
I don't do this kind of work, so I can't necessarily answer this with any kind of authority, but I would assume you would have to adjust the clock/data delay in the circuit by adjusting the size/speed of the transistors to move the setup-hold window (25ps) around a bit.
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