Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The voltage for latching VL and the holding voltage VH are related to the V/I slope or ESR of the Thyristor which can be estimated from the datasheet V/I drop using IL and IH.
Yes, there will be a minimum voltage, but its difficult to define.
The minimum holding current depends upon the current gains within the device, which is the actual latching mechanism. Be aware that this is highly temperature dependant and there can be considerable variation from device to device in minimum holding current.
The applied voltage at which latching gain falls below unity will also be temperature dependant. Its a very problematic area in which to try to nail down specifics.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.