hold violations in physical compiler

[rogger123]

hi,
I am synthesizing my RTL using DC. after the initial compile with actual functional clocks i am doing an incremental compile by removing all functional clocks and defining only one clock the "scan clock". I also get DC to fix all hold time violation on this clock.

i write out the netlist and move to physical compiler.
this is where my doubts are centered.
when i use physical compiler (PC) to read my netlist and the DEF file (floorplan)do i also need to read in all the constraints that i applied to my original RTL which i read into DC (eg clock definations etc)
i am only using physopt - some of the options

the next thing is after doing one round of physopt do i need to remove all my design clocks and create one new clock the "scan clock" as i did in DC and run physopt again?

i have tried doing the above mentioned flow. when i run physopt the second time by removing my functional clocks and defining a new scan clock. PC reports heaps of hold time violations and starts adding beffers to fix these violations. but in DC it never reported the violations.
are these violations a result of PC placing the cells in a manner which wud result in hold time violations in PC but not in DC?
am i gettingsomething worng or everythign wrong??

rgds
rogger

 

[eda_wiz]

Yes its required to use all your DC constraints for PC also(unless you writing out netlist as .db file,which has ur origianl constraints) .... Getting hold violations in PC are OK(may be DC cudnt find it becoz of the incorrect wireload model)... since PC has the PDEF placement information it can predict the timing well. But its better to fix hold violations in PnR, if its minor... if its major u may fix in PC/DC.... Also its Better to use RTL2PG flow in PC rather than using DC and G2PG in PC..One paper says RTL to Placed gates flow resulted in lesser area.....compared to DC and G2PG with PC..

in ur case .. say since DC didnt find a hold violation , it might have used a higher drive FF .. while fixing this PC may add buffers instead of downsizing the FF. which results in more area and power than RTL2PG flow...

 

[rogger123]

hi,
when i do the rtl2placed gates flow pc does not report any hold time violations.
but when i run the whole design thru DC and write out the netlist and read it thru pc with the same constraints why shud pc report hold violations. when dc has already used FF with high drive to eliminate hold violations.wouldn't PC use those same scan replaced and violation free flip flops that Dc has inserted?
which i presume it should and if that is the case it shud not report any violations....
rgds
rogger