Jul 26, 2012 #1 A anandmanivannan Newbie level 4 Joined Apr 26, 2012 Messages 6 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,320 I have flops in the design whose clocks are gated by other flop outputs. Due to this, hold violations occur during ATPG. What are the precautions that we should take when we use a clock that is gated by flip flop outputs.
I have flops in the design whose clocks are gated by other flop outputs. Due to this, hold violations occur during ATPG. What are the precautions that we should take when we use a clock that is gated by flip flop outputs.
Jul 26, 2012 #2 H harerama Member level 4 Joined Sep 21, 2011 Messages 79 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,288 Location Bangalore,India Activity points 1,747 I dont no exactly using "double synchronization" technic solve setup and hold violations
Aug 14, 2012 #3 dftrtl Banned Joined Feb 1, 2011 Messages 347 Helped 76 Reputation 152 Reaction score 74 Trophy points 1,308 Location Bangalore Activity points 0 Generate enable on negedge flop or use icg (latch plus AND gate)