For the chain with issues, ignore the scanout data from the certain point(you said you identified the flop with hold viol).
For the chains other than the one with issues, ignore all the flops that are within a logic cone starting at the flop with hold viols and beyond in the troubled chain.
Create a pattern with alternating 0s and 1s. The shift it in and out of our chip and remove effects of scan inversions. Then analyze bits near flip-flop with hold violation. Is it always the same as the value scanned into the flip-flop that feeds it in the chain? Then the effect is that you have 1 less flip-flop in the chain.
You could also analyze the timing reports where you have the failure. Determine if the value captured by the flip-flop is unknown or the same value loaded into the feeding flip-flop in the chain.
Why do you think all the data comes oen cycle ahead ? You have a big mistake in understanding here since unless you TOTALLY screw up the timing analysis, hold viols in silicon is very subtle and it may violate or may not violate depending on many factors like IR drop and process corner and such.Ok.. let me repeat....
Issue is present on Silicon and I have identified the flop with hold violation (not a metastability), so the expected data is coming one cycle ahead..
Then what would be the solution w.r.t. atpg.
Why do you think all the data comes oen cycle ahead ? You have a big mistake in understanding here since unless you TOTALLY screw up the timing analysis, hold viols in silicon is very subtle and it may violate or may not violate depending on many factors like IR drop and process corner and such.
Like I said, it's very simple. You cannot trust any data throught he failing flop. THat's all and nothing else. You have to set the tool to ignore those data potetially corrupted. There is no solution other than that.
How does modifying netlist help ? You still need to mask some registers.Hi,
Let me answer, By modifying the netlist for failing flop we can re-generate the patterns and validate the silicon , this is one method.
So like this I wanted to know is their any other method/soltions present to test the silicon.
How does modifying netlist help ? You still need to mask some registers.
If you have a hold viol on a flop which happens to an extent that it always violate, the hold viols must be quite great and the timng analysis was done totally wrong. With such a lousy timing analysis, I can assure you that there are so many more flops grossly violating the hold time and you won't be able to handle the test in a way you described.
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