I have to implement the 20ms ,50W Hold up circuit in my design.The voltage is 12V.Based on this, I implemented the MOSFET with 220mF capacitor based Hold up circuit.While simulating the circuit,the cathode of D1 waveform is different from capacitor output.Altenatively,If I replace the diode instead of MOSFET,Im getting the proper output.
Can you pls explain the reason behind this?
Attached the circuit and waveform.
Thanks for your reply.I have to implement 20ms hold up time at load.The 20ms is amount of time taken to reach from 12V to 9V.Hence I used 220mf capacitor.I used 5ohms to provide the minimum possible charging time for 220mF capacitor and which gives the charging time as 1.1s.
My question here is,when the power supply is turning of ,the current flow from capacitor will go to RL as well as power supply.Is there any other way to avoid current flow back to the power supply when the power supply is turned off condition.
I used the below methods to avoid this:
1.Added the diode instead of MOSFET( solved the problem.But unnecessary ~2W PD in normal working condition).
2.Immediate turning of the MOSFET when the power supply is turned OFF by properly controlling the Gate voltage.Not solved the issue that Im facing now
3.Added the additional MOSFET in series with this MOSFET.Not solved.
Any other method to address this issue
Thanks-Arumugam
Your circuit isn't well considered. The PMOS transistor will stay on as long as V(output) is above Vth and discharge the capacitor to input voltage source.
Hi,
As per the below formula,I believe the 43.28mf capacitor is needed.Can you pls explain ,how 18uF capacitor solve my requirement.
Total Capacitance = 2 x P x Δt / (η x (V122 – V222))
where :
P = power at the load
Δt =hold-up time required
η = converter efficiency
V1 = charged capacitor voltage before power drop out
V2 = final input voltage before power supply shut down.
Given data:
P 50 W
Δt 2.00E-02 S
η 0.75
V12 12 V
V22 9 V