ranaya
Advanced Member level 4
Dear All,
I have a pipelined design that was placed and routed in Innovus in MMC view. So the setup and hold views are based on worst and best corner libraries respectively. Starting from bc_wv view, the design was incrementally optimized (pre/post CTS) and the final post route optimization was done in the mode called OCV. Both postRoute timeDesign (Innovus) and Primetime STA have validated that the design is free of setup (WC .sdf) / hold (BC .sdf) violations.
But the post route simulation in NVSIM with annotated typical.sdf (extracted from Innovus after setting the design to typical view) and the post layout netlist gives me hold time violations. I've checked the clock constraints in testbench and they seem to be okay. Design does not have multiple clock domains, nor cross clocking. The simulation over the typical conditions is intended for the power analysis. Any possible explanation for this behavior ? Or am I missing a switch in simulator ?
PS: However I had the same clock uncertainty defined in both synthesis and P&R and clock propagated mode on. i.e. Could this be a reason ?
Thanks and BR
Anuradha
I have a pipelined design that was placed and routed in Innovus in MMC view. So the setup and hold views are based on worst and best corner libraries respectively. Starting from bc_wv view, the design was incrementally optimized (pre/post CTS) and the final post route optimization was done in the mode called OCV. Both postRoute timeDesign (Innovus) and Primetime STA have validated that the design is free of setup (WC .sdf) / hold (BC .sdf) violations.
But the post route simulation in NVSIM with annotated typical.sdf (extracted from Innovus after setting the design to typical view) and the post layout netlist gives me hold time violations. I've checked the clock constraints in testbench and they seem to be okay. Design does not have multiple clock domains, nor cross clocking. The simulation over the typical conditions is intended for the power analysis. Any possible explanation for this behavior ? Or am I missing a switch in simulator ?
PS: However I had the same clock uncertainty defined in both synthesis and P&R and clock propagated mode on. i.e. Could this be a reason ?
Thanks and BR
Anuradha