Hold time problem with Verilog netlist

[liujingshu]

hold time problem

Hi,guy,
My verilog netlist have hold time problem, but this problem happen at the very begining even before the reset signal, at the time the code still unwork. Do you think I have to fix this problem?

 

[xuanzhu]

hold time problem

Before the reset signal, any internal and output signal state is unstable and unknown. Could you tell us why you focus on it.
I think you should focus on the timing after reset and clock oscillating

 

[semi_jl]

hold time problem

Yes, I think you may not care it.

 

[liujingshu]

hold time problem

I think this problem should me ignored. Thanks your reply

 

[Thomson]

Re: hold time problem

I think this problem should me ignored. Thanks your reply

You shall check your verification strategy whether it's compatible with the actual conditions!


Thomson

 

[Elias.xie]

hold time problem

That's the point! If without reset, it also can work, then you must handle it, I think.

 

[funster]

Re: hold time problem

you needn't fix those hold time problem before reset signal,

because after reset, everything will be fine.

best regards

Hi,guy,
My verilog netlist have hold time problem, but this problem happen at the very begining even before the reset signal, at the time the code still unwork. Do you think I have to fix this problem?

 

[kgeorge123]

Re: hold time problem

Yes you do not have to worry about Hold time or high impedances or any Xs in the simulation before the start of reset. The simulation is dependent on the design libraries we are using. However in real chip nothing matters before reset.
Thats what we did in our simulations and ofcourse the chip is fine.