Hold time for level triggered D flip-flop

[A.Anand Srinivasan]

In flip-flops i heard of setup time and hold time for level triggered D flip-flop
i was able to understand about setup time but i couldn't understand hold time can someone explain it

 

[verilog_coder]

hold time

hold time is the time for which the input of the flip flop have to maintain its state after the flip flop samples.

 

[IanP]

Re: hold time

A positive hold time indicates a time after the active edge of clock, a negative hold time, before.

(hold time at pin of whole chip) =
(hold time of flip-flop data pin)
+ (max clock delay from chip pin to FF pin)
- (min data delay from chip pin to FF pin)

**broken link removed**
http://www.hardware-guru.com/Interview\D_FlipFlop.pdf

Regards,
IanP

 

[eda_freak]

Re: hold time

first of all a level triggered device is a latch and an edge triggered device a flip-flop..now the input needs to be stable for some time after clock edge in order to obtain correct output....ul learn about this if u study the architechture of a flip-flops...now flip-flop designs are there which do not even have the concept of hold time, they have only setup time requirement...u can read more about the setup and holdtime concepts in metastability. im attaching a doc on it...