Hold&Sample with switch capacitors

[mdpe]

Hi there! I need some help to get started with a project.

I have to design a simple sample and hold (S/H) stage. The S/H comprises a buffer amplifier and a sampling switch with a sampling capacitor (10MHz). The amplifier buffers the input so that the capacitor voltage must settle to within 1% of ideal final value.

To begin with I want to design the buffer amplifier, I need certain gain so that the settling error is less than the specified value and unity gain bandwidth so that the settling takes place within the defined sample duration.

Should I start with a 2-stages Op amp or 1-stage? I know I need to take into account Ro, output swing, slew rate etc. But i'm a bit lost!

thanks

 

[chris.mourad]

Hi

To get a <1% error on a DC voltage (e.g. 1V), this means that your open-loop gain should be at least 100 (meaning 40dB). This would lead to a tolerated error or offset of 10mV maximum.
--> This could be done with 1 stage amplifier

Now if I understand correctly, your system is switching at 10MHz, that is the sample frequency. Do you have any constraint on size and value of the capacitor?
--> To get that fast settling, you need to have a closed loop response with Unity gain frequency 2 times higher at least than the switching frequency. And this will depend on the current you can burn, the slew rate, etc...

 

[mdpe]

Right! That's a very good start point! Thanks a lot!

So the Op amps need to be at least twice as fast as the Fc (Nyquist). I have fix cap of 2pF. I need to design the "switch" transistors, bear in mind if it is in saturation or in the triode region.

One doubt I have is whether Ro of op amp affect the speed of the RC switch capacitor. As I see it, the capacitor have Rds and Ro(op amp) in series, so τ=(Rds+Ro)C. Does it need to be as fast as the Op amp?

Thanks!!

 

[erikl]

I have to design a simple sample and hold (S/H) stage. The S/H comprises a buffer amplifier and a sampling switch with a sampling capacitor (10MHz). The amplifier buffers the input so that the capacitor voltage must settle to within 1% of ideal final value.

To begin with I want to design the buffer amplifier, I need certain gain so that the settling error is less than the specified value and unity gain bandwidth so that the settling takes place within the defined sample duration.

The gain of your buffer amplifier is defined by the ratio of the max. voltage at its output (i.e. max. input voltage for the following circuit, e.g. an ADC), to the max. input voltage of your buffer amplifier. To achieve an error <1%, the open loop gain of this amplifier must be >100 times larger than the adjusted closed loop gain at your operating frequency.

To load the S/H capacitor to an error <1%, you need the propagation delay time of your amplifier + >4.6 (= -ln(1%)) RC time constants, R being this buffer amplifier's output impedance, C the capacitance to be driven (= buffer's output capacitance + S/H capacitance + parasitics).

 

[mdpe]

The thing is that I have the "switch resistor" transistor besides the output resistance of the op amp to charge the capacitance. I need RC to be small, therefore R need to be small. I'm not quite sure these two resistors are in parallel or series. I think they're in series, but, could you help me out? There's a picture in the first post if I didn't explain well enough.

If they're in parallel, it's all right. I can have just one-stage amplifier with high output resistance.
If they're in series I should have a very low output resistance and change my amplifier.

thanks!!

 

[D.A.(Tony)Stewart]

Don't use ceramic caps, they have a memory effect. Use a small film cap for the S&H cap.

You can work out the RpC leakage rate for sag and RsC capture rate for sample and choose values according to speeds, noise and rates required. Analog CMOS MUX switches are preferred with low glitch feedthru noise.

broken link removed

 

[erikl]

... I'm not quite sure these two resistors are in parallel or series. I think they're in series, but, could you help me out? There's a picture in the first post ...

If they're in parallel, it's all right. I can have just one-stage amplifier with high output resistance.
If they're in series I should have a very low output resistance and change my amplifier.

Apparently (up to your picture in the first post) they are in series. However your amp is designed as a buffer (gain=1), so might have sufficiently low output impedance.