Hold Flip Flop with async clear

[nishantgaidhani]

Hello everyone,

This is my first post in EDA board so wish me best luck ;-)
I wanted to know what is Flip Flop with data hold and async clear.
How it is useful in digital design? any advantages over normal FF?

Thanks in advance,
Nishant

 

[Ajish Babu S]

Asynchronous clear response is not depend on clock it will clear the output when the clear pin is active.
Synchronous clear is active only in the next active clock

 

[lambtron]

How it is useful in digital design? any advantages over normal FF?

The advantage of asynchronous clear is this: the initial state can be set even if there is no clock.

This is useful in many situations. For example, suppose the FF is controlling a solenoid and the FF, in turn, is controlled by a cpu. You don't want the solenoid to randomly activate (or not) when power is first applied to the circuit, before the cpu is able to turn off the FF. To prevent this, you connect the asynchronous system reset to the FF so that the FF will be cleared (and the solenoid will be inactive) upon power-up, even if the cpu crashes and never gets around to turning off the solenoid.

 

[nishantgaidhani]

Thanks Ajish and Lambtron for the explanation.

I think I should have given background to explain what I was looking for.
I was reading some topic releted to die size reduction in ASIC design and following is the relevent excerpt.
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Std cell library could be extended with more complex functions:for example a flip-flop with data hold and asynchronous clear. Currently same functionality can be created by using clock gating techniques in combination with existing flip-flops (with asynchronous clear only). Such 'design tricks' save area, power and improve speed.
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and I think I got the answer. It tells if library has complex functions readily available then you need not creat it using some odd logic and it saves area and power.

Please let me know of I'm not on track....
Thanks,
Nishant