Yes, 1b will be the worst hold check.
Because at rise edge 7, launch flop launching the data and at the same time capture flop capturing the data (launched in the previous clk edge)and If there is very small (or no) delay between two flops or if there is clock skew between them then capturing flop will not capture the right data or there may be race condition. That is why 1b will be the worst hold check.
tclk-q+tcomb (or +tnet) < thold , will lead to a race condition
tclk-q - clock to q delay of ff1(launch flop)
tcomb - comb delay between the flops
tnet - interconnect delay between the flops
So in order to avoid race condition, tclk-q+tcomb(or +tnet) > thold