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Even if you fix the hold violations in the synthesis stage, they may arise in the PnR flow. The true status of the hold violations will be available only after CTS since we use ideal clock till then. Usually, hold violations can be fixed by inserting delay elements in the data path. So we are least bothered about hold violations in the synthesis stage. What we worry about in the synthesis stage is the set up violations. If we are unable to fix the set up violations at this stage, we may not be able to fix them in the PnR stage. In such a case, we will have to change our logic of the design!!