# hold analysis during synthesis

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#### sun_ray

How to dump the hold report during synthesis. Which command and what options to be used? Is it necessary to do hold analysis during synthesis? How can hold violation be fixed during synthesis?

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#### sharath666

Hold reports are not generated during synthesis. But you can have a look by using -min option with the report_timing command...

cyrax747

### cyrax747

Points: 2

#### sun_ray

So hold report can be generated during synthesis by putting report_timing with -min option. Is not it?

Yes............

#### sun_ray

How does this hold report generated during synthesis help? How can we fix hold violations during synthesis?

Regards

#### biju4u90

##### Full Member level 3
Even if you fix the hold violations in the synthesis stage, they may arise in the PnR flow. The true status of the hold violations will be available only after CTS since we use ideal clock till then. Usually, hold violations can be fixed by inserting delay elements in the data path. So we are least bothered about hold violations in the synthesis stage. What we worry about in the synthesis stage is the set up violations. If we are unable to fix the set up violations at this stage, we may not be able to fix them in the PnR stage. In such a case, we will have to change our logic of the design!!

#### kumar_eee

We usually dont check the Hold till the Clock-tree is built. The main reason is, for the Hold, we need to know the exact Skew vaule.

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