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Histogram equalization hardware diagram for implementation in verilog hdl

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vickyuet

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dear all,

I know the working of histogram equalization algorithm, but i need to implement it in verilog HDL.The problem is that i am unable to draw
the hardware level diagram/design of algo but i am sure i can implement it on HDL once i got the working diagram.

Can anyone give me the hardware diagram of histogram equalization diagram?

Regards,
 

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