Please may I offer more info, we think this dual cascaded buck converter is bogus...do you agree?
...We have received a 300w dual cascaded buck converter (vin=120vdc to 400vdc; vout=100vdc) that does not work, we are being asked to make it work, but I think this circuit is a bogus design…please offer your opinion?
(its for a 170degc ambient measurement while drilling application.)
Please find attached the ltspice simulation of it and the pdf schematic. For comparison, it is simulated alongside a fictitious single stage buck for the same spec.
As you know, a cascade of SMPS’s would rarely be more efficient than a single SMPS, since the power is processed twice. In this case, with the high Vin, it was possible that the goal was to reduce the “power density in any single semiconductor”…in this case, the switching FET of the upstream buck, due to the fact that it suffers a large switching loss, due to the high vin of 400vdc.
However, when compared to a single stage buck converter, this is not necessarily the case at all. Please find attached a comparitive simulation of the cascaded bucks, and a single stage buck SMPS.
The upstream buck of the cascade is in DCM when at 400vin, the “advantage” of the cascade is seen in that the VDS of the upstream FET swings fully from 400V to 0V. (That is, it swings either side of its (intermediary) output voltage. This creates the opportunity to switch the fet on when its vds is zero. However, this would require a zero-crossing detector circuit, and no such thing exists here, and with the semiconductor limitation of MWD, this isn’t a likely possibility.
As such, its entirely possible that the fet could be switched on with its vds voltage being fully 400v. –In such a case, the circuit would have no advantage over a single stage buck converter….and would be more inefficient.
If we look at the comparitive simulation, it shows that the vds of the fet in the single stage only swings about 200v down from 400v, thus there is not such a possibility for reduced switch-on loss…however, the possibility would exist. The problem again is that there is no minimum drain voltage detection.
Also, demonstrated in the simulation is a dual “parallel” buck smps, which is, as you know, more efficient than a cascade or single buck. As you know, the parallel current paths mean a halving of conduction losses. There would not be sharing issues if they both use the one controller as per the sim.
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Other situations.
PNP turn off:
Also noted was that the PNP turn off circuit had a 10R resistor connected Base-emitter. As you know, this could potentially result in damage to the PNP turn-off as Vbe max is about 5v. As you know, the PNP turn-off is best connected with the diode Base-emitter.
Current sense transformer:
This is wound on an E-type core with mating halves. As you know, GDT’s are best wound bifilar on torroids using TIW if necessary.
Dead time
The RT/CT combination of the UCC28C43 is 59600R/2n2. This give a minimum off time of just 500ns. This is going to require a very high reset voltage for the CST. As you know, the CT cap should be increased and the RT reduced, since the discharge current in the ucc18c43 is 8.4mA.
This will also help the situation with the hi side fet drives.
Sync fets
Two sync fets, and that complex drive circuitry, seems excessive, since the worst case diode av. current in the single stage circuit is 2.2A, -could be done with a few parallel sic (PTC) diodes.
Slope compensation
The lower 120vin to 100vout situation would need slope compensation if done in CCM. However, I cannot see any slope compensation at the first viewing. With the low frequency setting, high vin, and low inductor values, it looks as if (deep) DCM was opted for, but this has the disadvantage of needing bigger inductor if peak current is too high, etc etc. It makes you wonder if they didn’t just opt for DCM because of the greater ease of feedback loop compensation.
Is this dual cascaded buck converter bogus?
the actual schematic has a 11.1uh inductor for the downstream buck inductor, but this would give ridiculously high peak current when vin=400vdc, I therefore made the downstream inductor bigger for this simulation.