Why? There is no need to avoid it. At least not for the drivers.To avoid the 0 to 5% range, I would need
Afaik there are cheap manufacturers shipping them with short delivery time all over the world. 1 week shouldn´t be a problem.And having PCBs professionally made isn't an option, because there is no company in my country making good ones, and having them made overseas incurs in either 4 month delays for postal shipping, or very high cost for courier shipping.
To avoid the 0 to 5% range, I would need
Why? There is no need to avoid it. At least not for the drivers.
Afaik there are cheap manufacturers shipping them with short delivery time all over the world. 1 week shouldn´t be a problem.
nternational Rectifier -> now a part of Infineon may have other interesting parts. And application notes. A good source of information.
What about digital PWM? --> good linearity.
What about "feedback" to improve linearity?
If you have a DCDC supply..why do you want undervoltage lockout?undervoltage lockout,
How can you think that the DCDC converter may be faulty, but at the same time think that the UVL circuit is not faulty?I want UVLO to be safe. You surely know Murphy's Laws? I try to defeat Murphy in my designs - not always with success, but mostly!
How can you think that the DCDC converter may be faulty, but at the same time think that the UVL circuit is not faulty?
Doesn't sound worthwhile for me. As someone who has spent years working with envelope-tracking RFPAs, modulating the RF power down to 0% isn't possible due leakage in the RFPAs. That will often define the lower end of your dynamic range, not the tracking supply.But in any case I do need to modulate down all the way to 0%, with decent linearity. To avoid the 0 to 5% range, I would need to add a high current, very low voltage negative supply, and that's not practical.
Hate to say this, but this is something you'll have to get over. The new, fast devices are small for good reason. My lab's etching setup is fairly simple but we can do 0.65mm pitch and 10mil traces with decent results.Also it's very uncomfortable for me to work with such chips that have 0.65mm pin pitch.
Interesting, I had considered using that chip in the past, but never got around to it. Was the duty cycle at least monotonic and smooth over the operating range? What about response time?The very reason why I'm building this from scratch is that I couldn't find ICs with enough performance, even for the individual blocks! For example I tried to use the LTC6992-1 as my PWM generator. That IC actually gets pretty well to the duty cycle extremes, but it's awfully nonlinear over the whole range, with several irregularities and zones of varying gain. It wasn't made for low distortion applications, of course, so I can't blame it - it's just not suitable for my use.
Doesn't sound worthwhile for me. As someone who has spent years working with envelope-tracking RFPAs, modulating the RF power down to 0% isn't possible due leakage in the RFPAs. That will often define the lower end of your dynamic range, not the tracking supply.
Hate to say this, but this is something you'll have to get over. The new, fast devices are small for good reason.
My lab's etching setup is fairly simple but we can do 0.65mm pitch and 10mil traces with decent results.
Interesting, I had considered using that chip in the past, but never got around to it. Was the duty cycle at least monotonic and smooth over the operating range? What about response time?
I've used the UCC35705 for high frequency PWM modulators before. Aside from that I've always done my own via discrete devices.
You should seriously consider using GaN FETs.
Some of EPC's dev boards use the Si8610BC in place of an optocoupler on some of the boards, so I presume it should work for your applications.
-Look at this DC-DC - cheap/small/very low C
https://power.murata.com/data/power/ncl/kdc_nxj1.pdf
-Look at isolated gate drivers which work on a different principle than the non-isolated level shifted ones you've been referring too (many UVLO options available):
**broken link removed**
-Or gate drivers optimized for GAN which must be fast
LM5113-Q1
FPGA PWM Generation
-See this thread I started on this topic:
https://www.edaboard.com/showthread.php?t=364633
-I settled on the basic shift register I proposed there plus a DDR register for 800Mhz resolution in a Xilinx 7 series
-Note that due to dithering (either by design or loop limit-cycling) output resolution can be higher than PWM resolution
Lastly did you explain why you need such a wide duty cycle? Normally you have an output voltage requirement and work backwards - choose a DC bus so you never need to go beyond 90 and 10 duty cycle.
In that case feedthrough likely won't be the bottleneck. But if you are modulating the RF input power, then you don't actually need tto back the bias down to zero in order to get your RF output down to zero. Why bother?and what's more important, I gave up the constant-amplitude drive of EER and instead I'm using proportional drive
We use a LV204 exposure system and Rota Spray etching tank from Mega Electronics. We use our own bath of NaOH for developing. Sensitized copper clad and ferric chloride from MG chemicals. For exposure we have used both plastic transparencies and heavy vellum tracing paper with an inkjet printer. Transparencies are easy to use but tracing paper gives better results (but are much harder to align for two layer boards).Can you give me some advice? I'm using an inkjet photo printer on Pictorico Ultra Premium film, transferring to positive presensitized board with the ink side down onto the board, between glass plates, exposing with a metal halide lamp to get something close to a point source for improved sharpness. The etchant is ferric chloride.
With 0.65mm parts I expect to make a few bridges here and there. If I'm feeling lazy, I just dump a blob a solder on them, then wick away the excess to leave behind decent joins.I have tried paste soldering with poor results at tiny pin spacings - too many shorts from excess solder, since it's so hard to apply just the right amount. So I tin the pads thinly, then apply flux and the parts, and reheat, but the results are still all over the place.
I've used it at 500KHZ and get pulse width down to 10ns and duty cycle up to 95% (tie the DISCH pin low).That IC doesn't seem well suited to my needs. It won't get close enough to 100% duty cycle, and while it's rated to get to 0%, there is no information about its linearity at very small duty cycles. Having a flipflop output, it very likely has a certain minimum pulse width, and snaps from there directly to zero.
Exactly, how did you guess?That one isn't well suited for the kind of silicon FETs I'm using, and also I wonder about the minimum pulse width requirement in the datasheet. Could it be that with shorter pulse widths it might lock up in the logic high state?
Well life is such that requirements are always in competition.
Linearity seems to demand wider supplies (or a full bridge topology instead of half).
Perhaps you can mitigate your voltage limit fears with a fast comparator circuit that disables gate drives if it sees anything outside 0-50V for example.
But if you are modulating the RF input power, then you don't actually need tto back the bias down to zero in order to get your RF output down to zero. Why bother?
We use a LV204 exposure system and Rota Spray etching tank from Mega Electronics. We use our own bath of NaOH for developing. Sensitized copper clad and ferric chloride from MG chemicals. For exposure we have used both plastic transparencies and heavy vellum tracing paper with an inkjet printer. Transparencies are easy to use but tracing paper gives better results (but are much harder to align for two layer boards).
With 0.65mm parts I expect to make a few bridges here and there. If I'm feeling lazy, I just dump a blob a solder on them, then wick away the excess to leave behind decent joins.
I've used it at 500KHZ and get pulse width down to 10ns and duty cycle up to 95% (tie the DISCH pin low).
>That one isn't well suited for the kind of silicon FETs I'm using, and also I wonder about the minimum pulse width requirement in the datasheet. Could it be that with shorter pulse widths it might lock up in the logic high state?
Exactly, how did you guess?
I'm skeptical... it's certainly not easy either way (especially without feeback), but when you modulate the supply to such a degree you're going to get a great deal of AM-PM due to nonlinearities in the FET Coss. And at some point VDS will be so low that the FET is going to be operating in its triode region, which will cause lots of AM-AM distortion. Unless you're also varying the Vgs bias, which opens up a whole other can of worms....To maintain linearity. I have tried approaches that combine envelope restoration in the mid and high part of the dynamic range with fixed-supply class AB at low signal levels, and have found it next to impossible to maintain good linearity on all bands and under all load conditions. Instead when fully modulating the supply voltage it's easy.
Never had this problem, personally. The system draws a vacuum to keep things nice and tight.That exposure box uses diffuse light. That provides even exposure, but if you get any separation between the board and the artwork, traces will narrow and even disappear.
I started using tracing paper based on advice I found on this website. Like it says, get the heaviest stuff you can find to avoid crinkling in the printer. The nice thing about vellum vs transparency is that the ink won't bead up due to surface tension.I will try using tracing paper. Anyway the Pictorico transparency isn't far from tracing paper. It's translucent but not clear, and the printer prints pretty well on it, configured for high quality photo paper.
My problem with that method is that if there is a short to any trace under the IC, it's over. I have to remove the IC to clear the short, and start over.
I don't see any reference to a FF in the datasheet for the LM5113. Though I certainly wouldn't be surprised if there is one in the high side level shifter. I believe I was the first one to report that silicon but in the LM5113, since then they've modified the datasheet to mention it, and released a new revision (LMG1205). But the new one is only available in a DSBGA package which even I don't want deal with....40 years doing electronics can teach one to read between the lines of datasheets. And any such IC using a flipflop to reconstruct the output pulse can suffer from this sort of problem. Those that don't usually employ an internal circuit that strictly enforces a sufficiently high minimum pulse width to keep the flipflop behaving.
I'm skeptical... it's certainly not easy either way (especially without feeback), but when you modulate the supply to such a degree you're going to get a great deal of AM-PM due to nonlinearities in the FET Coss. And at some point VDS will be so low that the FET is going to be operating in its triode region, which will cause lots of AM-AM distortion.
Unless you're also varying the Vgs bias, which opens up a whole other can of worms....
Never had this problem, personally. The system draws a vacuum to keep things nice and tight.
I started using tracing paper based on advice I found on this website. Like it says, get the heaviest stuff you can find to avoid crinkling in the printer. The nice thing about vellum vs transparency is that the ink won't bead up due to surface tension.
I don't see any reference to a FF in the datasheet for the LM5113. Though I certainly wouldn't be surprised if there is one in the high side level shifter.
I believe I was the first one to report that silicon but in the LM5113, since then they've modified the datasheet to mention it, and released a new revision (LMG1205). But the new one is only available in a DSBGA package which even I don't want deal with....
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