High Q circuit Simulation

[farshaddd]

Hi every one.

I'm simulating a very high quality factor RLC circuit in cadence.
The AC analysis is OK (correct answer) if I take a very small frequency step size.

However, the transient analysis is not correct (even with very small time step size) !!!!!.
I should mention that the TRAN analysis is performed in resonant frequency (8.563 kHz).
What should I do?

The circuit schematic has been attached.
Thanks a lot.

 

[LvW]

Quote from Microsims Application notes.
"The simulation run must a minimum of Q cycles before the circuit reacts....
For a crystal with moderately high-Q (20000) it can take close to a million cycles before the oscillator reaches a steady state condition.....
But it is possible to use AC analysis to simulate high-Q circuits"

 

[dick_freebird]

tran has sloppy tolerances that can let solvers "lose track of" minuscule-amplitude activity before it can "bloom out of the noise".

Simulating XOs is a special art, this what I have learned from failed test chips after successful (looking) analyses. And high enough Q starts to look like the same problem-set.

 

[mtwieg]

I can't speak to cadence, but I know LTspice also has issues with tran simulations of high Q circuits. Usually it's just a matter of setting the maximum timestep very low (like <<1/(Q*fc)) and allowing it plenty of time to reach steady state (like >> Q/fc). I think this has worked for Q values as high as 500, but at some point I assume other factors like numerical precision and charge/voltage tolerances would matter as well.

For your circuit with a Q of ~200,000,000, I don't know what you'd have to do to get "real" results, but I'm not sure how useful it is to simulate such an unrealistic system anyways...

A harmonic balance or periodic steady state solution might be better suited for you.

 

[dick_freebird]

What is your stimulus source's initial voltage?

If it isn't in the center (zero crossing) of the sine
then you have a built in initial offset which will
average away over time (but never completely
settle).

The schematic looks like LTSpice, not Virtuoso.