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High power offline Flyback with no primary RCD or D/Z clamp

coffeefet

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Hi,
Why do all the datasheet and app note schematics of high power offline flybacks with FSCQ1565 cotroller show no primary clamp whatsoever?
They only show a small Drain source capacitor, which they call the "resonant capacitor".
(which is true but it hardly seems big enough to quench leakage spiking for cases of overload, etc)
The internal FET is only 650V rated.

FSCQ1565 datasheet (pg 19 schem)

App note for FSCQ1565 (AN4146) (pg 19 schem)
 

Velkarn

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hi!
mosfet can take this spike in avalanche mode, so probably this designs made with such spike management
--- Updated ---

and the resonant cap is forming proper oscillation in "no current" time (this is the QR-fly)
 
Z

zenerbjt

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Thanks, yes i suppose it must be relying on the avalanch of the FET..but surely this is a poor situation?
The FSCQ1565RT datasheet does say max VDS of the internal FET is 650V.
So you woudl think they are indicating that relying on avalanche is not recomended.

I believe a FET is slightly and cumulatively damaged every time it avalanches?
 

Velkarn

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The FSCQ1565RT datasheet does say max VDS of the internal FET is 650V.
So you woudl think they are indicating that relying on avalanche is not recomended.
lots of mosfet datasheets rate vds voltage and single and repetitive avalanche energy... this is not a contradiction
--- Updated ---

I believe a FET is slightly and cumulatively damaged every time it avalanches?
no, if single and repetitive avalanche energy limits are not exceeded
--- Updated ---

1610724603686.png
 

Easy peasy

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It's a bad design all round - except if the L-leak on the Tx and the res cap cause the ringing to go down to 0 volt - giving zero loss turn on ( zero current spike at turn on ) - however this will result in a resonant rise in volts at turn off - and will require a 700V fet to tolerate this ....
 

coffeefet

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Thanks, i must admit i'm stunned by the 93W offline flyback schematic of page 19 of the App note in post #1 above.
There is no primary clamp whatsoever.
That design would surely be classed a gross designer irresponsibility?
The internal fet in FSCQ1565 is only 650V rated.
 

treez

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no, if single and repetitive avalanche energy limits are not exceeded
Yes but coffeefet cannot use avalanche mode because the FSCQ1565 datasheet does not state the "repetitive avalanche rating" for the internal FET.
 

treez

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Also, coffeefet is onto a looser here, because page 13 of the FSCQ1565 datasheet says that adding the drain_source capacitor is good for EMC.
This just is not correct, because it worsens EMC due to the fact that when the FET turns ON, the drain_source capacitance is suddenly discharged, resulting in a discharge current spike which worsens EMC.
The datasheet says that the slower rising drain voltage at FET turn-OFF reduces EMC problems, but it doesnt , because it worsens EMC at FET turn-ON time. You cannot reduce EMC problems in a flyback by simply adding a drain source capacitance....if only life were so easy.
 

treez

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Also, from page 14 of the FSCQ1565 datasheet, it is evident that at maximum load, the switching frequency must be less than 45kHz, otherwise the converter will get stuck in extended quasi resonant operation.
That is a very big restriction and means a large transformer will be needed.
 

treez

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Looking at the Offline flyback schem of page 19 of AN41-46 (below), would you agree that the voltage spike which appears on the 1nF drain_source capacitor is basically that voltage on the 1nF capacitor which occurs when 0.5*L(leak)*Ipeakpri^2 = 0.5*C*V^2
(in other words the energy in the leakage inductor at FET-switch-off-instant will transfer into the 1nF drain_source capacitor and charge it up...giving the leakage voltage spike

Where V is the leakage spike voltage.

This will “sit” on top of Vin +V(referred_to_pri).

App note for FSCQ1565 (AN4146) (pg 19 schem)
https://www.onsemi.com/pub/Collateral/AN-4146.pdf.pdf
 

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