High Level CPLD Question

[mikez]

I apologize in advance for not being a technical guy, but I have a question about using CPLD's. I'm working on a PC-based application that involves counting pulses from 50-60 different sensors (pulses may be coming from sensors as quickly as every 350 microseconds or so). I was hoping to offload a lot of the I/O tasks from the PC onto a CPLD, and then have the PC just read counts from the CPLD. The PC will be running a RTOS, and needs to be updated with current sensor counts every 500 microseconds. Is this kind of an architecture feasible?

Any direction would be greatly appreciated!

 

[vishwa]

Hi

I couldn't understand your problem in clear. What i got from your words is you need a switch like circuit to select one among many sensors data. It is possible with a CPLD at such a higher frequency.


If you are able to explain your problem in simple words, then you will get a solution soon from so many experted techies.

Regards,
Vishwa

 

[mami_hacky]

In my idea your architecture is feasible,

What is the minimum pulse width?
Are these pulses synchronous with each other? Or completely asynchronous?
PC reads the counters every 500us? Pulse come in the intervals of 350us? Then you will pass a for example 6 bit counter to the pc which shows the total number of received pulses in this period. ok?

 

[echo47]

What type of interface between the CPLD and the PC?

I assume you mean that *every* sensor outputs pulses at 350us rate.

Does your RTOS guarantee 500us rate with no occasional longer delays? Is 350us the fastest pulse rate? If yes, then each sensor outputs no more than two pulses per RTOS read, so two-bit counters would be sufficient. 60 input synchronizers plus 60 two-bit counters seems doable in medium or large CPLD, although I would select a small FPGA such as Spartan-3.

 

[mikez]

What is the minimum pulse width?
Are these pulses synchronous with each other? Or completely asynchronous?
PC reads the counters every 500us? Pulse come in the intervals of 350us?

Sorry about the confusion...The minimum pulse width is 350us. The minimum off time is also 350us, so I guess the shortest pulse period would be 700us. The pulses are completely asynchronous.

Theoretically, all of the sensors could be generating pulses at the same time. Because of the placement of the sensors though, no more than 8 sensors will be generating pulses at the same time.

Does your RTOS guarantee 500us rate with no occasional longer delays?

Actually, I haven't selected a RTOS yet, so I'm not sure. Based on the sensor counts, the PC needs to be able to compute a vehicle's position every 500us. I'm assuming that I should be able to find a RTOS that guarantees the ability to read counts and compute position every 500us, but like I said, I'm not much of a technical expert. :wink: Do you think this will be a problem?

If yes, then each sensor outputs no more than two pulses per RTOS read, so two-bit counters would be sufficient. 60 input synchronizers plus 60 two-bit counters seems doable in medium or large CPLD, although I would select a small FPGA such as Spartan-3

Two-bit counters sound safe. An FPGA sounds good too...is there any reason in particular to consider an FPGA over a CPLD?

 

[renato]

Hi Mikes ...

Why did you not consider to use a Microcontroler instead of a CPLD ? You could use uC to acquire signals and it could transmit to PC via RS232 or USB interface (more expensive).

Maybe you have to use a simple combinational logic or a high I/O uC. Anyway if you need to use a period of about 700us you have to use a dedicated hardwre to treat the signals and send it for PC or use a very dedicated OS. For example, Windows by defaut work if longer than 10ms. I don't know about POSIX systems. However for a uC it is easy.

It is just one more idea

Regards

 

[echo47]

Have you selected an interface between between the CPLD and the PC? Sounds like you need to read at least 240 kilobits/sec (60 channels of two bits every 500us).

A small FPGA has roughly similar cost to a medium-large CPLD, and the FPGA is vastly more flexible (plenty of room to grow). However the FPGA requires an external configuration PROM.

renato - microcontroller probably no good because the project has 50-60 pulse inputs, not just one.

 

[mikez]

Why did you not consider to use a Microcontroler instead of a CPLD ? You could use uC to acquire signals and it could transmit to PC via RS232 or USB interface (more expensive).

Actually, my original plan was to use PC / PIC combination (or to just use a PC by itself, if possible). There are PICs that can handle 60+ inputs. A friend suggested I look into a CPLD though. One problem with the PIC is communicating enough information to the PC every 500us (assuming RS232).

Have you selected an interface between between the CPLD and the PC? Sounds like you need to read at least 240 kilobits/sec (60 channels of two bits every 500us).

No, I haven't selected an interface between the CPLD and the PC yet, so any suggestions are welcome. You're right though...I was estimating at least 240K baud.