You're probably talking about a tri-state output circuit. Take for instance the example attached. If a=0 and b=0 you would have Vout≈Vcc (cause M1 would be cutoff and M2 would be on triode region) which corresponds to a logic 1. If a=Vcc and b=Vcc Vout≈0 (cause M2 would be cutoff and M1 would be on triode region) which corresponds to a logic 0. If a=0 and b=Vcc both M1 and M2 would be on triode region so Vout≈Vcc/2. There would be a very small resistance value between Vcc and GND (almost shorcut) so try avoiding this. NOW!! if a=Vcc and b=0 both M1 and M2 are on cutoff region so the impedance value you get from your output into your circuit would be VERY VERY high.
This is used on circuits which share the same output (Vout) to avoid load effects. Try to think that the attached circuit is the output stage of a memory which shares the same bus with an ADC to comunicate with a processor. If the ADC what's to "talk" to the procesor, the memory should not be trying to talk at the same time cause shortcuts could occur, so the memory is on HIGH IMPEDANCE state during the time the ADC is expressing itself.
Hope I made myself clear,
diemilio.