High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

[FvM]

The circuit shows low Q bandpass characteristic now. The problems mentioned in post #9 are still not addressed. You get forward biased bulk junctions of M1, M2 and M11. Respectively Cdb1 can't act as feedback capacitor.

The solution can be either to use SOI transistors or review literature for CMOS bandpass circuits, e.g. the 0.18 µm filter in quote 20.

 

[promach]

The solution can be either to use SOI transistors or review literature for CMOS bandpass circuits, e.g. the 0.18 µm filter in quote 20.

Do you mean **broken link removed** ?

Do you know of any suitable SOI transistor model ?

 

[FvM]

Yes, that seems to be the paper quoted in lit. 20.

Unfortuantely I'm not in the IC design business and don't have models.

 

[promach]

See https://www.leti-cea.com/cea-tech/leti/english/Pages/Applied-Research/Facilities/UTSOI.aspx , https://www.elsevier.com/books/indu...l-bsim-img-for-ic-design/hu/978-0-08-102401-0 and https://bsim.berkeley.edu/models/bsimimg/

 

[promach]

For **broken link removed** , why do the gate nodes for M3 and M4 reaches kilo-Volt level ?

 

[FvM]

You are sourcing 4 x 1 µA from Vdd and sinking 2 x 1 µA to ground, without any load. Respectively the connected nodes are floating high.

 

[promach]

No, the real root cause of the kilo-volt issue is Vdd voltage source should be modified to have value of "PWL(0 0 1n 3.3)" , instead of just 3.3V

Now, the next question is how to modify the inputs Vin1 and Vin2 to test the bandpass nature of the circuit ?

I am not sure about the ways to determine the passband, ripple or cutoff frequency of this particular circuit.

 

[FvM]

No, the real root cause of the kilo-volt issue is Vdd voltage source should be modified to have value of "PWL(0 0 1n 3.3)" , instead of just 3.3V

Don't think that you understand much about the behavior of your circuit. The only difference with PWL source is that the node voltages float slowly beyond VDD instead of starting at kV. Still completely unrealistic.

 

[promach]

The latest schematics that I have could only show highpass characteristics, not bandpass.

 

[FvM]

The AC analysis is running with Vdd=0 due to PWL source. Another useless simulation setup.

 

[promach]

@FvM I have modified according to your advice.

See the attached LTSpice circuit file

However, the bandpass peak still have some issue with gain.

 

[FvM]

I don't recognize circuit features that set a reasonable bias point. Did you check the bias point?

 

[promach]

Any comment on the following circuit besides high power consumption (45uW) ?

 

[promach]

1) why the increase of both current source values will increase the centre frequency ?

2) are there ways other than increasing current source (which increases power consumption) ?

3) I suppose the gyrator used in this active cmos bandpass filter circuit is a shunt inductor ? So, how does this actually lead to bandpass filtering effect ?

4) I am trying to study about the following. Could anyone explain about it ?