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High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

promach

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For High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS , how to derive expressions (1c) and (1d) ?

1. For expression (1c) : Cgs2 and Cdb5 are not in parallel with Cgd5 and Cgd1 . Besides, how to obtain (1+ gm2/gm3)*Cgd2 ?

2. For expression (1d) : Cgd4 and Cgd6 are not in parallel with Cdb4, Cdb6 and Cbs1


--- Updated ---

I tried to replicate the cmos bandpass filter circuit, but it does not seem to work for now.

Anyone found any mistake in the circuit ?

 

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Dominik Przyborowski

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1. For expression (1c) : Cgs2 and Cdb5 are not in parallel with Cgd5 and Cgd1 . Besides, how to obtain (1+ gm2/gm3)*Cgd2 ?

2. For expression (1d) : Cgd4 and Cgd6 are not in parallel with Cdb4, Cdb6 and Cbs1
1. Small signal analysis principle - all independent sources are replaced by their internal resistances.
2. Miller effect

Circuit seems to be simulated in CMOS, while design was done in FD-SOI. There is an important difference between both processes.
 

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What about (1+ gm2/gm3)*Cgd2 ?
 

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but why is gm2/gm3 equivalent to the gain factor ?
--- Updated ---

okay, I got it now. gain for the M2 common source amplifier is equivalent to gm2*Rout where Rout = 1/gm3 since M3 is diode-connected mosfet
 

Dominik Przyborowski

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If you draw small signal model of this branch and calculate gain, you will see.

It is always a good excersise to draw model schematics and calculate things. Thanks to this, we can understand more.
 

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You only quote the first lines of the paper's circuit analysis, hence we can't see how the intended band pass function is achieved and which parameters determine it. Respectively we can only guess which parameters are different in your implementation.

To check the function of your circuit, you would
1. Check the bias point
2. verify gm and C parameters
3. verify loop gain
 

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Dominik Przyborowski

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Usually the reason is simple - invalid designer ;)

First of all, in CMOS you cannot use bulk connections like in FD-SOI. In CMOS, every Vbs>0.3V will cause high current injection into your circuit and deteriorate bias points. So, M11 and M2 connections are not proper.

Second, in paper is stated twice shorter L for devices, it means they might be 4 times faster, so filter frequency in your case might be located ca 0.25GHz instead of 1GHz as in paper. However you are showing simulation result for frequency up to 10GHz in linear scale. Even, if the circuit was working, it would not be visible.

Finally, in paper authors are using 1V supply, which for they case is 25% higher than nominal, while you are using also 1V, which is 55% lower than nominal. Simply, operating points of devices in your circuit might be wrong due to lack of headroom.
 

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Finally, in paper authors are using 1V supply, which for they case is 25% higher than nominal, while you are using also 1V, which is 55% lower than nominal.
Wait, why 55% lower than nominal ?
 

Dominik Przyborowski

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Also in CMOS, loop like here from output to bulk will not be working as well (or be at least lousy).
You need to split M1 to two in parallel with gate of second connected to o2, which i believe is your output instead of o1.
 

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the paper author stated that o1 is the filter output terminal.
 

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You see using 180nm process. Nominal supply for it is 1.8V
I suppose it is not mandatory to use 1.8V for 180nm process.
 

Dominik Przyborowski

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Yes, it is not mandatory, however maybe authors has a reason to use supply higher than nominal?
Have you enough supply for headroom?
 

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Why is 1.8V the nominal voltage for 180nm process ?

And I just tried using 1.8V*1.25 = 2.25V , but the circuit is still not working yet.
 

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The following small signal expressions seems very tedious to derive ?

 

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It seems that I forgot the diode connection for M3, but this cmos bandpass filter circuit still does not work out for me even after the mistake correction. Why ?

 

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