Hiya Keith!
Don't give up on your H-bridge yet... [while I haven't checked your driver circuit in detail for appropriate 'dead-time' (guard bands between drive applied to the separate phases) generation], there were a couple of dubious aspects about the design of the MOSFET gate drive circuits that might warrant a closer look.
Have a peek at the TI app note: **broken link removed**, as it describes some of the design considerations when driving MOSFETs in applications like yours.
For starters, I'd be wary of the series 1N914 diodes D5-D8 in your schematic. While I can see you're trying to avoid significant reverse bias of the gate, they also prevent the removal of the gate charge and will extend the FET switch-off times considerably. This will lead to rail-to-rail shorts (and possibly dead FETs) when the opposite phase is energised.
On the same note, why have you included C7-C10 (100 pF)? As far as I can tell, these will only serve to worsen the FET switching characteristics. Likewise the 22K resistors (R2,3,10,11) are much too high, forming a discharge time constant far exceeding (1/ultrasonic switching frequency) given the ~1 nF of MOSFET gate capacitance.
While I suspect with some attention to redesigning the H-bridge drive circuitry it will fit your needs nicely, another method commonly used is a step-up transformer with series inductance (to resonate away the transducer capacitance). Although much lower powered than your application, you can see the concept applied in the schematic here:
http://kitsrus.com/projects/k126.pdf
Some extra food for thought: There are dedicated bridge driver ICs available (such as
G5 HVIC: Next Generation HVIC Platform) which *greatly* simplify HV bridge design. Maybe one of these might help out...?
Good luck!