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High fanout - how to deal with this warning?

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vivek_p

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High fanout..........

module Memory (clk, we, rd_addr1, rd_addr2, wr_addr, wr_data, rd_data1, rd_data2,stall);
`define DATA_WIDTH 8
`define ADDR_LEN 8
`define DEPTH 255

input clk;
input we; // Write enable
input [`ADDR_LEN-1:0] rd_addr1; // address to read first operand.
input [`ADDR_LEN-1:0] rd_addr2; // address to read second operand.
input [`ADDR_LEN-1:0] wr_addr; // address to write the data.
input [`DATA_WIDTH-1:0] wr_data; // data to be written into the memory, coming from the ALU.
input stall;

output [`DATA_WIDTH-1:0] rd_data1; // first operand read from memory.
output [`DATA_WIDTH-1:0] rd_data2; // second operand read from memory.

wire clk;
wire we;
wire [`ADDR_LEN-1:0] rd_addr1;
wire [`ADDR_LEN-1:0] rd_addr2;
wire [`ADDR_LEN-1:0] wr_addr;
wire [`DATA_WIDTH-1:0] wr_data;
wire [`DATA_WIDTH-1:0] rd_data1;
wire [`DATA_WIDTH-1:0] rd_data2;
wire stall;

reg [`DATA_WIDTH-1:0] mem [`DEPTH-1:0];

always @ (posedge clk)
begin
if (we && ~stall)
mem[wr_addr]<= wr_data;
end
// Read operation
assign rd_data1= mem[rd_addr1];
assign rd_data2= mem[rd_addr2];
endmodule


----------------------------------------------------------------

When I complied this design in Synopsys I got the following warning...................

Warning: Design 'Data_Mem' contains 5 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'N18': 1052 load(s), 1 driver(s)
Net 'N25': 1038 load(s), 1 driver(s)
Net 'N26': 1080 load(s), 1 driver(s)
Net 'N27': 1109 load(s), 1 driver(s)
Net 'clk': 1976 load(s), 1 driver(s)

Can anyone help me in solving this issue
 

kumar_eee

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High fanout..........

Why don't you try something like Register duplication?.

I'm sorry to say that I've limited knowledge on this.
 

    vivek_p

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shitansh

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Re: High fanout..........

Hi,

Which tool are you using for synthesis.

In case of Actel's tool you need to rout clock and reset to global network (since clock and reset are always candidate for high fanout drivers), and for that you need to pass clock and reset signals to global buffer before use them.

If you dont do this, warning may be flags, again its depends on synthesis tool you are using.

Hth
Shitansh Vaghela
 

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