vivek_p
Advanced Member level 4
High fanout..........
module Memory (clk, we, rd_addr1, rd_addr2, wr_addr, wr_data, rd_data1, rd_data2,stall);
`define DATA_WIDTH 8
`define ADDR_LEN 8
`define DEPTH 255
input clk;
input we; // Write enable
input [`ADDR_LEN-1:0] rd_addr1; // address to read first operand.
input [`ADDR_LEN-1:0] rd_addr2; // address to read second operand.
input [`ADDR_LEN-1:0] wr_addr; // address to write the data.
input [`DATA_WIDTH-1:0] wr_data; // data to be written into the memory, coming from the ALU.
input stall;
output [`DATA_WIDTH-1:0] rd_data1; // first operand read from memory.
output [`DATA_WIDTH-1:0] rd_data2; // second operand read from memory.
wire clk;
wire we;
wire [`ADDR_LEN-1:0] rd_addr1;
wire [`ADDR_LEN-1:0] rd_addr2;
wire [`ADDR_LEN-1:0] wr_addr;
wire [`DATA_WIDTH-1:0] wr_data;
wire [`DATA_WIDTH-1:0] rd_data1;
wire [`DATA_WIDTH-1:0] rd_data2;
wire stall;
reg [`DATA_WIDTH-1:0] mem [`DEPTH-1:0];
always @ (posedge clk)
begin
if (we && ~stall)
mem[wr_addr]<= wr_data;
end
// Read operation
assign rd_data1= mem[rd_addr1];
assign rd_data2= mem[rd_addr2];
endmodule
----------------------------------------------------------------
When I complied this design in Synopsys I got the following warning...................
Warning: Design 'Data_Mem' contains 5 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'N18': 1052 load(s), 1 driver(s)
Net 'N25': 1038 load(s), 1 driver(s)
Net 'N26': 1080 load(s), 1 driver(s)
Net 'N27': 1109 load(s), 1 driver(s)
Net 'clk': 1976 load(s), 1 driver(s)
Can anyone help me in solving this issue
module Memory (clk, we, rd_addr1, rd_addr2, wr_addr, wr_data, rd_data1, rd_data2,stall);
`define DATA_WIDTH 8
`define ADDR_LEN 8
`define DEPTH 255
input clk;
input we; // Write enable
input [`ADDR_LEN-1:0] rd_addr1; // address to read first operand.
input [`ADDR_LEN-1:0] rd_addr2; // address to read second operand.
input [`ADDR_LEN-1:0] wr_addr; // address to write the data.
input [`DATA_WIDTH-1:0] wr_data; // data to be written into the memory, coming from the ALU.
input stall;
output [`DATA_WIDTH-1:0] rd_data1; // first operand read from memory.
output [`DATA_WIDTH-1:0] rd_data2; // second operand read from memory.
wire clk;
wire we;
wire [`ADDR_LEN-1:0] rd_addr1;
wire [`ADDR_LEN-1:0] rd_addr2;
wire [`ADDR_LEN-1:0] wr_addr;
wire [`DATA_WIDTH-1:0] wr_data;
wire [`DATA_WIDTH-1:0] rd_data1;
wire [`DATA_WIDTH-1:0] rd_data2;
wire stall;
reg [`DATA_WIDTH-1:0] mem [`DEPTH-1:0];
always @ (posedge clk)
begin
if (we && ~stall)
mem[wr_addr]<= wr_data;
end
// Read operation
assign rd_data1= mem[rd_addr1];
assign rd_data2= mem[rd_addr2];
endmodule
----------------------------------------------------------------
When I complied this design in Synopsys I got the following warning...................
Warning: Design 'Data_Mem' contains 5 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'N18': 1052 load(s), 1 driver(s)
Net 'N25': 1038 load(s), 1 driver(s)
Net 'N26': 1080 load(s), 1 driver(s)
Net 'N27': 1109 load(s), 1 driver(s)
Net 'clk': 1976 load(s), 1 driver(s)
Can anyone help me in solving this issue