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Hierarchical STA Sign-Off flow deploying Interface

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Hierarchical STA Sign-Off flow deploying Interface
Logic Modelling (ILM)
Werner Braun
(wbr@toshiba.de)
Technology/CAE group
Toshiba Electronics Europe GmbH
Hansaallee 181, D-40549 Düsseldorf, Germany


1. Abstract
High complexity of today's designs is one of the predominant problems in ASIC
implementation and verification. In the past years we have seen more often several
EDA tools reaching their performance limits. As a consequence a "new" methodology
became state of the art for the verification and implementation of multi million gate
designs. Therefore EDA vendors need to offer a hierarchical application of their tools,
and likewise silicon vendors need to implement these utilities seamless in their ASIC
sign-off flows.
This paper focuses on hierarchical methodologies in static verification deploying
Synopsys PT Interface Logic Modelling capability. It describes how these modelling
abstraction can be used within a static timing sign-off flow. Also, it will compare the
different abstraction methodologies, highlighting pro's and con's and indicating the
application types for which they are best suited, because there is no push bottom
solution which covers all types of designs.
 

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