Hierarchical block <U0> is unconnected in block <DSB_TOP>

[tsillen]

Implementation of SIGNAL -> FIR FILTER -> DAC;
Works fine in simulation, is matlab generated filter but because of the following warning
"WARNING:Xst:1290 - Hierarchical block <U0> is unconnected in block <DSB_TOP>. It will be removed from the design."

And I can't seem to figure out what is wrong; searched on the internet, tried all kind of things but I can't seem to fix the problem ...

Top level:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity DSB_TOP is
    port(
        clk         :   in  STD_LOGIC;
        cs          :   out STD_LOGIC;   
        ldac        :   out STD_LOGIC;  
        pd          :   out STD_LOGIC; 
        we          :   out STD_LOGIC;
        dac_out :   out STD_LOGIC_VECTOR(11 downto 0)
        );
end DSB_TOP;
 
architecture DSB_TOP of DSB_TOP is
-- CLK DIV.
component clkdiv is
    port(
        clk             :   in STD_LOGIC;
        clk_out     :   out STD_LOGIC;
        clk_out1        :   out STD_LOGIC;
 
        reset           :   out STD_LOGIC;
 
        clock_en    :  out STD_LOGIC
 
        --clk_out2      :   out STD_LOGIC
        );
end component;
 
-- ADC
 
component ADC
    port(
 
        clk             : in  STD_LOGIC;
 
      adc_out       : inout  STD_LOGIC_VECTOR (11 downto 0)
 
        );
        
end component;
-- DAC
component DAC
    port(
        clk_in      :   in  STD_LOGIC;
        dac_in      :   in  STD_LOGIC_VECTOR(11 downto 0);
        cs              :   out     STD_LOGIC;  -- Chip select signal 
        ldac            :   out     STD_LOGIC;  -- Load ADC 
        pd              :   out     STD_LOGIC; -- low power mode 
        we              :   out     STD_LOGIC;  -- write enable
        dac_out     :   out     STD_LOGIC_VECTOR(11 downto 0)
        );
end component;
 
-- FILTER
component filter IS
   PORT( 
        clk         :   in    std_logic; 
      clk_enable    :   in    std_logic; 
      reset         :   in    std_logic; 
      filter_in :   in    std_logic_vector(11 DOWNTO 0); -- sfix12_E1
      filter_out    :   out   std_logic_vector(11 DOWNTO 0)  -- sfix12_E1
        );
END component;
 
 
 
signal clock_en : STD_LOGIC;
 
signal reset : STD_LOGIC;
 
signal clk_out : STD_LOGIC;
 
signal clk_out1 : STD_LOGIC;
 
signal adc_out :std_logic_vector(11 DOWNTO 0); -- sfix12_E1
 
signal dac_in :std_logic_vector(11 DOWNTO 0); -- sfix12_E1
begin
    U1: clkdiv
        PORT MAP(
            clk => clk,
            clk_out => clk_out,
            clk_out1 => clk_out1,
 
            reset => reset
 
            --clk_out2 => clk_out2
        );
    U2: DAC
        PORT MAP(
            clk_in => clk_out, --48kHz clock
            cs => cs,
            ldac => ldac,
            pd => pd,
            we => we,
            dac_out => dac_out,
            dac_in => dac_in
        );
 
    U0: filter
        PORT MAP(
            clk => clk_out,
         clk_enable => clock_en,     
         reset => reset,       
         filter_in => adc_out,                
         filter_out => dac_in    
        );
 
    U4: ADC
        PORT MAP(
            clk => clk_out1,
            adc_out => adc_out
        );
 
 
end DSB_TOP;

---

Clk div code:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity clkdiv is
    port(
        clk         :   in STD_LOGIC;
        clk_out :   out STD_LOGIC;
        clk_out1    :   out STD_LOGIC;
        reset       :   out STD_LOGIC;
        clock_en    :   out STD_LOGIC := '1'
        --clk_out2  :   out STD_LOGIC
        );
end clkdiv;
 
architecture clkdiv of clkdiv is
signal q:STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal lock : STD_LOGIC := '0';
begin
-- clock divider
    process(clk)
    begin if clk'event and clk = '1' then
            q <= q + 1;
            if q = "000000001000000000000000" and lock = '0' then --reset generator for filter
                reset <= '1';
                lock <= '1';
                end if;
        end if;
    end process;
    --clk_out <= q(12); -- ~6103.52 Hz
    --clk_out <= q(10); -- ~6103.52 Hz
    clk_out <= q(9); -- ~48828.13 Hz
    clk_out1 <= q(13);
    --clk_out1 <= q(10);    -- ~24414.06 Hz
    --clk_out1 <= q(11);    -- ~12k
    --clk_out2 <= q(0); -- ~25MHz
end clkdiv;

---

Adc code:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity ADC is
    Port ( clk : in  STD_LOGIC;
           adc_out : inout  STD_LOGIC_VECTOR (11 downto 0) := (others => '0'));
end ADC;
 
architecture Behavioral of ADC is
begin
    process(clk)
    begin
    if rising_edge(clk) then
        adc_out <= NOT adc_out;
    end if;
    end process;
end Behavioral;

---

Filter code (matlab generated):

---

Code VHDL - [expand]
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-- -------------------------------------------------------------
--
-- Module: filter
-- Generated by MATLAB(R) 9.1 and the Filter Design HDL Coder 3.1.
-- Generated on: 2017-04-09 02:05:07
-- -------------------------------------------------------------
 
-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- OptimizeForHDL: on
-- TargetDirectory: C:\Users\Thijs\Desktop\poepfilter
-- RemoveResetFrom: ShiftRegister
-- SerialPartition: 42
-- TestBenchStimulus: impulse step ramp chirp noise
 
-- -------------------------------------------------------------
-- HDL Implementation    : Fully Serial
-- Folding Factor        : 42
-- -------------------------------------------------------------
-- Filter Settings:
--
-- Discrete-Time FIR Filter (real)
-- -------------------------------
-- Filter Structure  : Direct-Form FIR
-- Filter Length     : 42
-- Stable            : Yes
-- Linear Phase      : Yes (Type 2)
-- Arithmetic        : fixed
-- Numerator         : s12,10 -> [-2 2)
-- Input             : s12,-1 -> [-4096 4096)
-- Filter Internals  : Specify Precision
--   Output          : s12,-1 -> [-4096 4096)
--   Product         : s12,-1 -> [-4096 4096)
--   Accumulator     : s12,-1 -> [-4096 4096)
--   Round Mode      : convergent
--   Overflow Mode   : wrap
-- -------------------------------------------------------------
 
 
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
 
ENTITY filter IS
   PORT( clk                             :   IN    std_logic;
         clk_enable                      :   IN    std_logic;
         reset                           :   IN    std_logic;
         filter_in                       :   IN    std_logic_vector(11 DOWNTO 0); -- sfix12_E1
         filter_out                      :   OUT   std_logic_vector(11 DOWNTO 0)  -- sfix12_E1
         );
 
END filter;
 
 
----------------------------------------------------------------
--Module Architecture: filter
----------------------------------------------------------------
ARCHITECTURE rtl OF filter IS
  -- Local Functions
  -- Type Definitions
  TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF signed(11 DOWNTO 0); -- sfix12_E1
  -- Constants
  CONSTANT coeff1                         : signed(11 DOWNTO 0) := to_signed(19, 12); -- sfix12_En10
  CONSTANT coeff2                         : signed(11 DOWNTO 0) := to_signed(34, 12); -- sfix12_En10
  CONSTANT coeff3                         : signed(11 DOWNTO 0) := to_signed(19, 12); -- sfix12_En10
  CONSTANT coeff4                         : signed(11 DOWNTO 0) := to_signed(-22, 12); -- sfix12_En10
  CONSTANT coeff5                         : signed(11 DOWNTO 0) := to_signed(-38, 12); -- sfix12_En10
  CONSTANT coeff6                         : signed(11 DOWNTO 0) := to_signed(-3, 12); -- sfix12_En10
  CONSTANT coeff7                         : signed(11 DOWNTO 0) := to_signed(28, 12); -- sfix12_En10
  CONSTANT coeff8                         : signed(11 DOWNTO 0) := to_signed(-1, 12); -- sfix12_En10
  CONSTANT coeff9                         : signed(11 DOWNTO 0) := to_signed(-51, 12); -- sfix12_En10
  CONSTANT coeff10                        : signed(11 DOWNTO 0) := to_signed(-31, 12); -- sfix12_En10
  CONSTANT coeff11                        : signed(11 DOWNTO 0) := to_signed(42, 12); -- sfix12_En10
  CONSTANT coeff12                        : signed(11 DOWNTO 0) := to_signed(44, 12); -- sfix12_En10
  CONSTANT coeff13                        : signed(11 DOWNTO 0) := to_signed(-51, 12); -- sfix12_En10
  CONSTANT coeff14                        : signed(11 DOWNTO 0) := to_signed(-91, 12); -- sfix12_En10
  CONSTANT coeff15                        : signed(11 DOWNTO 0) := to_signed(25, 12); -- sfix12_En10
  CONSTANT coeff16                        : signed(11 DOWNTO 0) := to_signed(130, 12); -- sfix12_En10
  CONSTANT coeff17                        : signed(11 DOWNTO 0) := to_signed(5, 12); -- sfix12_En10
  CONSTANT coeff18                        : signed(11 DOWNTO 0) := to_signed(-221, 12); -- sfix12_En10
  CONSTANT coeff19                        : signed(11 DOWNTO 0) := to_signed(-121, 12); -- sfix12_En10
  CONSTANT coeff20                        : signed(11 DOWNTO 0) := to_signed(447, 12); -- sfix12_En10
  CONSTANT coeff21                        : signed(11 DOWNTO 0) := to_signed(1024, 12); -- sfix12_En10
  CONSTANT coeff22                        : signed(11 DOWNTO 0) := to_signed(1024, 12); -- sfix12_En10
  CONSTANT coeff23                        : signed(11 DOWNTO 0) := to_signed(447, 12); -- sfix12_En10
  CONSTANT coeff24                        : signed(11 DOWNTO 0) := to_signed(-121, 12); -- sfix12_En10
  CONSTANT coeff25                        : signed(11 DOWNTO 0) := to_signed(-221, 12); -- sfix12_En10
  CONSTANT coeff26                        : signed(11 DOWNTO 0) := to_signed(5, 12); -- sfix12_En10
  CONSTANT coeff27                        : signed(11 DOWNTO 0) := to_signed(130, 12); -- sfix12_En10
  CONSTANT coeff28                        : signed(11 DOWNTO 0) := to_signed(25, 12); -- sfix12_En10
  CONSTANT coeff29                        : signed(11 DOWNTO 0) := to_signed(-91, 12); -- sfix12_En10
  CONSTANT coeff30                        : signed(11 DOWNTO 0) := to_signed(-51, 12); -- sfix12_En10
  CONSTANT coeff31                        : signed(11 DOWNTO 0) := to_signed(44, 12); -- sfix12_En10
  CONSTANT coeff32                        : signed(11 DOWNTO 0) := to_signed(42, 12); -- sfix12_En10
  CONSTANT coeff33                        : signed(11 DOWNTO 0) := to_signed(-31, 12); -- sfix12_En10
  CONSTANT coeff34                        : signed(11 DOWNTO 0) := to_signed(-51, 12); -- sfix12_En10
  CONSTANT coeff35                        : signed(11 DOWNTO 0) := to_signed(-1, 12); -- sfix12_En10
  CONSTANT coeff36                        : signed(11 DOWNTO 0) := to_signed(28, 12); -- sfix12_En10
  CONSTANT coeff37                        : signed(11 DOWNTO 0) := to_signed(-3, 12); -- sfix12_En10
  CONSTANT coeff38                        : signed(11 DOWNTO 0) := to_signed(-38, 12); -- sfix12_En10
  CONSTANT coeff39                        : signed(11 DOWNTO 0) := to_signed(-22, 12); -- sfix12_En10
  CONSTANT coeff40                        : signed(11 DOWNTO 0) := to_signed(19, 12); -- sfix12_En10
  CONSTANT coeff41                        : signed(11 DOWNTO 0) := to_signed(34, 12); -- sfix12_En10
  CONSTANT coeff42                        : signed(11 DOWNTO 0) := to_signed(19, 12); -- sfix12_En10
 
  -- Signals
  SIGNAL cur_count                        : unsigned(5 DOWNTO 0); -- ufix6
  SIGNAL phase_41                         : std_logic; -- boolean
  SIGNAL phase_0                          : std_logic; -- boolean
  SIGNAL delay_pipeline                   : delay_pipeline_type(0 TO 41); -- sfix12_E1
  SIGNAL inputmux_1                       : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL acc_final                        : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL acc_out_1                        : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL product_1                        : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL product_1_mux                    : signed(11 DOWNTO 0); -- sfix12_En10
  SIGNAL mul_temp                         : signed(23 DOWNTO 0); -- sfix24_En9
  SIGNAL prod_typeconvert_1               : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL acc_sum_1                        : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL acc_in_1                         : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL add_temp                         : signed(12 DOWNTO 0); -- sfix13_E1
  SIGNAL output_typeconvert               : signed(11 DOWNTO 0); -- sfix12_E1
  SIGNAL output_register                  : signed(11 DOWNTO 0); -- sfix12_E1
 
 
BEGIN
 
  -- Block Statements
  Counter_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      cur_count <= to_unsigned(41, 6);
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        IF cur_count = to_unsigned(41, 6) THEN
          cur_count <= to_unsigned(0, 6);
        ELSE
          cur_count <= cur_count + 1;
        END IF;
      END IF;
    END IF;
  END PROCESS Counter_process;
 
  phase_41 <= '1' WHEN cur_count = to_unsigned(41, 6) AND clk_enable = '1' ELSE '0';
 
  phase_0 <= '1' WHEN cur_count = to_unsigned(0, 6) AND clk_enable = '1' ELSE '0';
 
  Delay_Pipeline_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      delay_pipeline(0 TO 41) <= (OTHERS => (OTHERS => '0'));
    ELSIF clk'event AND clk = '1' THEN
      IF phase_41 = '1' THEN
        delay_pipeline(0) <= signed(filter_in);
        delay_pipeline(1 TO 41) <= delay_pipeline(0 TO 40);
      END IF;
    END IF;
  END PROCESS Delay_Pipeline_process;
 
  inputmux_1 <= delay_pipeline(0) WHEN ( cur_count = to_unsigned(0, 6) ) ELSE
                     delay_pipeline(1) WHEN ( cur_count = to_unsigned(1, 6) ) ELSE
                     delay_pipeline(2) WHEN ( cur_count = to_unsigned(2, 6) ) ELSE
                     delay_pipeline(3) WHEN ( cur_count = to_unsigned(3, 6) ) ELSE
                     delay_pipeline(4) WHEN ( cur_count = to_unsigned(4, 6) ) ELSE
                     delay_pipeline(5) WHEN ( cur_count = to_unsigned(5, 6) ) ELSE
                     delay_pipeline(6) WHEN ( cur_count = to_unsigned(6, 6) ) ELSE
                     delay_pipeline(7) WHEN ( cur_count = to_unsigned(7, 6) ) ELSE
                     delay_pipeline(8) WHEN ( cur_count = to_unsigned(8, 6) ) ELSE
                     delay_pipeline(9) WHEN ( cur_count = to_unsigned(9, 6) ) ELSE
                     delay_pipeline(10) WHEN ( cur_count = to_unsigned(10, 6) ) ELSE
                     delay_pipeline(11) WHEN ( cur_count = to_unsigned(11, 6) ) ELSE
                     delay_pipeline(12) WHEN ( cur_count = to_unsigned(12, 6) ) ELSE
                     delay_pipeline(13) WHEN ( cur_count = to_unsigned(13, 6) ) ELSE
                     delay_pipeline(14) WHEN ( cur_count = to_unsigned(14, 6) ) ELSE
                     delay_pipeline(15) WHEN ( cur_count = to_unsigned(15, 6) ) ELSE
                     delay_pipeline(16) WHEN ( cur_count = to_unsigned(16, 6) ) ELSE
                     delay_pipeline(17) WHEN ( cur_count = to_unsigned(17, 6) ) ELSE
                     delay_pipeline(18) WHEN ( cur_count = to_unsigned(18, 6) ) ELSE
                     delay_pipeline(19) WHEN ( cur_count = to_unsigned(19, 6) ) ELSE
                     delay_pipeline(20) WHEN ( cur_count = to_unsigned(20, 6) ) ELSE
                     delay_pipeline(21) WHEN ( cur_count = to_unsigned(21, 6) ) ELSE
                     delay_pipeline(22) WHEN ( cur_count = to_unsigned(22, 6) ) ELSE
                     delay_pipeline(23) WHEN ( cur_count = to_unsigned(23, 6) ) ELSE
                     delay_pipeline(24) WHEN ( cur_count = to_unsigned(24, 6) ) ELSE
                     delay_pipeline(25) WHEN ( cur_count = to_unsigned(25, 6) ) ELSE
                     delay_pipeline(26) WHEN ( cur_count = to_unsigned(26, 6) ) ELSE
                     delay_pipeline(27) WHEN ( cur_count = to_unsigned(27, 6) ) ELSE
                     delay_pipeline(28) WHEN ( cur_count = to_unsigned(28, 6) ) ELSE
                     delay_pipeline(29) WHEN ( cur_count = to_unsigned(29, 6) ) ELSE
                     delay_pipeline(30) WHEN ( cur_count = to_unsigned(30, 6) ) ELSE
                     delay_pipeline(31) WHEN ( cur_count = to_unsigned(31, 6) ) ELSE
                     delay_pipeline(32) WHEN ( cur_count = to_unsigned(32, 6) ) ELSE
                     delay_pipeline(33) WHEN ( cur_count = to_unsigned(33, 6) ) ELSE
                     delay_pipeline(34) WHEN ( cur_count = to_unsigned(34, 6) ) ELSE
                     delay_pipeline(35) WHEN ( cur_count = to_unsigned(35, 6) ) ELSE
                     delay_pipeline(36) WHEN ( cur_count = to_unsigned(36, 6) ) ELSE
                     delay_pipeline(37) WHEN ( cur_count = to_unsigned(37, 6) ) ELSE
                     delay_pipeline(38) WHEN ( cur_count = to_unsigned(38, 6) ) ELSE
                     delay_pipeline(39) WHEN ( cur_count = to_unsigned(39, 6) ) ELSE
                     delay_pipeline(40) WHEN ( cur_count = to_unsigned(40, 6) ) ELSE
                     delay_pipeline(41);
 
  --   ------------------ Serial partition # 1 ------------------
 
  product_1_mux <= coeff1 WHEN ( cur_count = to_unsigned(0, 6) ) ELSE
                        coeff2 WHEN ( cur_count = to_unsigned(1, 6) ) ELSE
                        coeff3 WHEN ( cur_count = to_unsigned(2, 6) ) ELSE
                        coeff4 WHEN ( cur_count = to_unsigned(3, 6) ) ELSE
                        coeff5 WHEN ( cur_count = to_unsigned(4, 6) ) ELSE
                        coeff6 WHEN ( cur_count = to_unsigned(5, 6) ) ELSE
                        coeff7 WHEN ( cur_count = to_unsigned(6, 6) ) ELSE
                        coeff8 WHEN ( cur_count = to_unsigned(7, 6) ) ELSE
                        coeff9 WHEN ( cur_count = to_unsigned(8, 6) ) ELSE
                        coeff10 WHEN ( cur_count = to_unsigned(9, 6) ) ELSE
                        coeff11 WHEN ( cur_count = to_unsigned(10, 6) ) ELSE
                        coeff12 WHEN ( cur_count = to_unsigned(11, 6) ) ELSE
                        coeff13 WHEN ( cur_count = to_unsigned(12, 6) ) ELSE
                        coeff14 WHEN ( cur_count = to_unsigned(13, 6) ) ELSE
                        coeff15 WHEN ( cur_count = to_unsigned(14, 6) ) ELSE
                        coeff16 WHEN ( cur_count = to_unsigned(15, 6) ) ELSE
                        coeff17 WHEN ( cur_count = to_unsigned(16, 6) ) ELSE
                        coeff18 WHEN ( cur_count = to_unsigned(17, 6) ) ELSE
                        coeff19 WHEN ( cur_count = to_unsigned(18, 6) ) ELSE
                        coeff20 WHEN ( cur_count = to_unsigned(19, 6) ) ELSE
                        coeff21 WHEN ( cur_count = to_unsigned(20, 6) ) ELSE
                        coeff22 WHEN ( cur_count = to_unsigned(21, 6) ) ELSE
                        coeff23 WHEN ( cur_count = to_unsigned(22, 6) ) ELSE
                        coeff24 WHEN ( cur_count = to_unsigned(23, 6) ) ELSE
                        coeff25 WHEN ( cur_count = to_unsigned(24, 6) ) ELSE
                        coeff26 WHEN ( cur_count = to_unsigned(25, 6) ) ELSE
                        coeff27 WHEN ( cur_count = to_unsigned(26, 6) ) ELSE
                        coeff28 WHEN ( cur_count = to_unsigned(27, 6) ) ELSE
                        coeff29 WHEN ( cur_count = to_unsigned(28, 6) ) ELSE
                        coeff30 WHEN ( cur_count = to_unsigned(29, 6) ) ELSE
                        coeff31 WHEN ( cur_count = to_unsigned(30, 6) ) ELSE
                        coeff32 WHEN ( cur_count = to_unsigned(31, 6) ) ELSE
                        coeff33 WHEN ( cur_count = to_unsigned(32, 6) ) ELSE
                        coeff34 WHEN ( cur_count = to_unsigned(33, 6) ) ELSE
                        coeff35 WHEN ( cur_count = to_unsigned(34, 6) ) ELSE
                        coeff36 WHEN ( cur_count = to_unsigned(35, 6) ) ELSE
                        coeff37 WHEN ( cur_count = to_unsigned(36, 6) ) ELSE
                        coeff38 WHEN ( cur_count = to_unsigned(37, 6) ) ELSE
                        coeff39 WHEN ( cur_count = to_unsigned(38, 6) ) ELSE
                        coeff40 WHEN ( cur_count = to_unsigned(39, 6) ) ELSE
                        coeff41 WHEN ( cur_count = to_unsigned(40, 6) ) ELSE
                        coeff42;
  mul_temp <= inputmux_1 * product_1_mux;
  product_1 <= resize(shift_right(mul_temp(21 DOWNTO 0) + ( "0" & (mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10) & NOT mul_temp(10))), 10), 12);
 
  prod_typeconvert_1 <= product_1;
 
  add_temp <= resize(prod_typeconvert_1, 13) + resize(acc_out_1, 13);
  acc_sum_1 <= add_temp(11 DOWNTO 0);
 
  acc_in_1 <= prod_typeconvert_1 WHEN ( phase_0 = '1' ) ELSE
                   acc_sum_1;
 
  Acc_reg_1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      acc_out_1 <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        acc_out_1 <= acc_in_1;
      END IF;
    END IF;
  END PROCESS Acc_reg_1_process;
 
  Finalsum_reg_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      acc_final <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF phase_0 = '1' THEN
        acc_final <= acc_out_1;
      END IF;
    END IF;
  END PROCESS Finalsum_reg_process;
 
  output_typeconvert <= acc_final;
 
  Output_Register_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      output_register <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF phase_41 = '1' THEN
        output_register <= output_typeconvert;
      END IF;
    END IF;
  END PROCESS Output_Register_process;
 
  -- Assignment Statements
  filter_out <= std_logic_vector(output_register);
END rtl;

---

Dac code:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity DAC is
--  TI TLV5919 DAC
    port(
        clk_in  :   in STD_LOGIC;
        dac_in  :   in STD_LOGIC_VECTOR(11 downto 0);
        cs          :   out STD_LOGIC;  -- Chip select signal
        ldac        :   out STD_LOGIC;  -- Load DAC
        pd          :   out STD_LOGIC; -- low power mode
        we          :   out STD_LOGIC;  -- write enable
        dac_out :   out STD_LOGIC_VECTOR(11 downto 0)
        );
end DAC;
 
architecture DAC of DAC is
begin
    process(clk_in)
    begin
    if rising_edge(clk_in) then
        dac_out <= dac_in;
    end if;
    end process;   
we      <= clk_in;  -- transparant output of clk to we
cs      <= '0';         -- chip always selected
ldac        <= '0';         -- double buffer not used
pd      <= '1';     -- high power mode
end DAC;

---

I have also attached the project to this post.

Any help or tips are greatly appreciated

 

[barry]

Probably got a file in the wrong directory

 

[tsillen]

I moved the filter files to the place where all the other files are but no luck.

 

[barry]

I think your problem might be that reset gets set to 1 in the clkdiv module and never gets cleared. Thus, the output of your filter will always be zero, and thus the logic is removed.

 

[ads-ee]

I think your problem might be that reset gets set to 1 in the clkdiv module and never gets cleared. Thus, the output of your filter will always be zero, and thus the logic is removed.

Barry is right, if you look at the filter code the reset is active high and you've set it to a constant 1 in the clkdiv module so the filter code is removed as it doesn't do anything.

 

[tsillen]

You guys are correct. I did that for a short moment for some reason. It was already in the late hours so I did not pay proper attention. Going to try it in the morning.