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Best Solution is "Assert RESET asynchronously and De-assert Synchronously"
Active Low or Active HIGH?
If active high reset is used, any noise on the reset line can cause a spike and this results in a reset. But if active Low reset is used, this can never happen. So active low is preferred. This is the case where the reset comes from external to chip, but if reset is internallly generated; then this may not be big issue.
Power point of view:
In cases where leakage is significant, active Low reset causes more leakage; as in in-active state the reset is active high and the transistor can leak slowly from high causing more leakage. So active high is preferred for low power.