Hi need some info on Static timing analysis

[noorullam]

Hi,
Can any one provide me some scenario's how to fix the setup and hold time violations. any material on static timing analysis

 

[omara007]

first .. u shoud not post such a question here .. but anyhow .. try to refer to the PrimeTime reference manual ..

 

[wadaye]

Hi noorullam,

Basicly, you can reduce the combinational logic level, recuce the capacitance of the pin, and load of the pin to fix setup violation.

And you can add buf to fix the hold violation. But when you meet them both in the

same path, you have to resynthesize or rerouting.

 

[avimit]

Hi,
Fixing the setup and hold violation depends upon your design and the how to do it will depend upon the tools you are using. Hold violations are generaly fixed by inserting buffers in the path which is failing. Setup fix is not that straight forward. you may try to change the drive strengths of the cells in the path which is failing.
Kr,
Aviral Mittal

 

[alban]

hai,
inform for static timing analysis