Hi,i want to know how to write good testbench,thank you!

[ppenday]

verilog by navabi is a good book to start with.

 

[viv_1005]

I would suggest you to use some Object Oriented concepts while developing your testbenches. Structure and re-use is among the best practices. This reduces the percentage of erroneous codes and increases the percentage of tested code.

 

[DonnaMitchell]

You can always try a graphical testbench generation tool to create your VHDL, Verilog or SystemC models. That way the model structure and connections are automatically created, and you just have to worry about the actual test data.

SynaptiCAD's TestBencher Pro creates test benches multiple timing diagrams and a description about how to apply the diagrams to the model under test. The tool creates an object oriented bus-functional model and gives you full control over the test senerios including random generation and golden reference model generation.

If you are looking for more simple stimulus based test benches, their WaveFormer Pro tool creates a stimulus based model from a single timing diagram. It is pretty easy to use because you just draw the waveforms and save the file to VHDL or Verilog. There is also an option to up grade to reactive test bench generation so the test bench will report errors during simulation.

These products can be downloaded from www.syncad.com

 

[uk]

is there any relation between writing testbenches and some script languages like perl, tclk, etcetera...

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