slava_edf
Newbie level 5
Prof. use Verilog/VHDL at last 5 yaer.
Design, synthesis, simulate and prototype in all developed pack Altera, Xillinx, Actel.
Design IP-core.
Embedded C/C++, Assembler at last 4 yaer.
PCB design.
my little project in blog page : https://project-ideas-yaroslav.blogspot.com/2012/09/simple-hdd-motor-controller-on-cpld.html
Looking for freelance job .
if I am interesting you send me message to message box
Design, synthesis, simulate and prototype in all developed pack Altera, Xillinx, Actel.
Design IP-core.
Embedded C/C++, Assembler at last 4 yaer.
PCB design.
my little project in blog page : https://project-ideas-yaroslav.blogspot.com/2012/09/simple-hdd-motor-controller-on-cpld.html
Looking for freelance job .
if I am interesting you send me message to message box
