HFSS solving on chip structure poor result at 10MHz

[neoflash]

Hi,

I'm simulating a metal pad on silicon die. The dimension is near 40um x 40um and distance to substrate is 7um.

The simulated capacitance is close to hand calculation but varies a lot over frequency. For some reason, I prefer to simulate at 10MHz.

Does HFSS have any issue near very low frequency?

Regards,
Neo

 

[volker@muehlhaus]

If you simulate the effective capacitance from a metal to the substrate, for a typical RFIC stackup with some oxide in between, the capacitance does vary with frequency. You have Cox in series with (Csub || Rsub), so that the effective capacitance is frequency dependent.

 

[neoflash]

If you simulate the effective capacitance from a metal to the substrate, for a typical RFIC stackup with some oxide in between, the capacitance does vary with frequency. You have Cox in series with (Csub || Rsub), so that the effective capacitance is frequency dependent.

the problem is the result changes every time I tighten convergence knob. I can have several percent variation from run to run.