billjoe
Member level 1
netlist simulation ise
I want to do back annotated simulation using Xiline ISE simulation model
first I need to compiler all .v in ~/unisims/*.v
but some .v file cannot be compiled
ex use ncverilog compile RAMR16_S2_S36.v
error :
ncvlog: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1671|25): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1671|41): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_reg[12:4]][addra_reg[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1679|25): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_reg[12:4]][addra_reg[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1679|41): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1686|25): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1686|41): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,EXPSMC (C:/NCSIM/unisims/RAMB16_S2_S36.v,1774|39): expecting a semicolon (';') [9.2.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1774|55): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,EXPSMC (C:/NCSIM/unisims/RAMB16_S2_S36.v,1780|42): expecting a semicolon (';') [9.2.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1780|58): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= dia_int;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1787|22): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= dia_int;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1787|38): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
ncvlog: Memory Usage - 2.7M data
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.5s, 8.8% cpu)
Q 1 . How to compile ~Xilinx/unisim/*.v ~Xilinx/simprim/*.v ~Xilinx/CoreGen/*.v
Q2 . How to use simulation model (Xilinx ISE generate) to do simulation (want to use ncverilog/vcs to generate .fsdb)?
Q3. Is there any tutortial about how to verify the ISE netlist is correct (use ISE netlist to do pre-sim in nvverilog )?
I want to do back annotated simulation using Xiline ISE simulation model
first I need to compiler all .v in ~/unisims/*.v
but some .v file cannot be compiled
ex use ncverilog compile RAMR16_S2_S36.v
error :
ncvlog: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1671|25): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1671|41): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_reg[12:4]][addra_reg[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1679|25): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_reg[12:4]][addra_reg[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1679|41): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1686|25): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1686|41): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,EXPSMC (C:/NCSIM/unisims/RAMB16_S2_S36.v,1774|39): expecting a semicolon (';') [9.2.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1774|55): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,EXPSMC (C:/NCSIM/unisims/RAMB16_S2_S36.v,1780|42): expecting a semicolon (';') [9.2.2(IEEE)].
doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2];
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1780|58): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= dia_int;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1787|22): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= dia_int;
|
ncvlog: *E,MISEXX (C:/NCSIM/unisims/RAMB16_S2_S36.v,1787|38): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
ncvlog: Memory Usage - 2.7M data
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.5s, 8.8% cpu)
Q 1 . How to compile ~Xilinx/unisim/*.v ~Xilinx/simprim/*.v ~Xilinx/CoreGen/*.v
Q2 . How to use simulation model (Xilinx ISE generate) to do simulation (want to use ncverilog/vcs to generate .fsdb)?
Q3. Is there any tutortial about how to verify the ISE netlist is correct (use ISE netlist to do pre-sim in nvverilog )?