Help with XSA 50 and Xilinx ISE 7.1i

[magnetra]

While generating the bit file of my design, i got this warning

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_23/_n0000 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 1 warnings.
Creating bit map...
Saving bit stream in "dsss.bit".
Bitstream generation is complete.

what do i make of it?
If my question is incomplete, please let me know why more info i need to provide.

Regards
M

 

[wolfheart_2001]

it means you use another combinational circuit to enable/disable the clock in your design...and the compiler advice you to use CE(clock enable) pin instead...so i think it would be better if you put your design in the forum to see where this warning come from

 

[magnetra]

Thanks, I solved the problem myself.
I realize that not all VHDL codes are synthesizable because some tend to violate DRC (Design Rule Check). The problem was a DRC violation. Now that I solved, the ckt is working fine.

M