Help with working in Xilinx ISE 5.1i

[Jayson]

This question pertains to the schematic entry method of doing a design.

How do I assign an input pad to a specific particular pin on my FPGA? How do I assign an output pad to another specific pin on my FPGA device? When I go to floorplanner it defaults to two pins.

Can someone maybe point me to a quick tutorial on how to do this using the schematic entry tools of XIlinx ISE 5.1i?

- Jayson

 

[my_garden]

I think ISE5.1's schematic tools isn't good
This tool is for HDL, you'd better use HDL
The below is the link of ISE5.1's manual
**broken link removed**

 

[Bartart]

>> How do I assign an input pad to a specific particular pin on my FPGA?

Use constraints file editor to create ucf file. Your "top" vhdl file has some so called port, this ports must be connected to phisical FPGA pins.

Example of the constraints file:

net ba loc=p137;
net saddr<0> loc=p141;

>>How do I assign an output pad to another specific pin on my FPGA device?

In schematic design when you add the IO marker you can select if it is input or output.

>>When I go to floorplanner it defaults to two pins.

Because you didn't set the pins in constraints editor.


Good luck, bart

 

[Jayson]

What good are FPGA's if when you turn the power off they lose the program?

- Jayson

 

[Bartart]

U can still use CPLD device.


Bart

 

[Jayson]

In commerical applications where are the programs stored?

- Jayson

 

[incognito]

In commerical applications where are the programs stored?

- Jayson

In any configuration memory, serial protocol for example do the job... xilinx ise got all the required tools for create rom content to implement in your memory.

Any low cost programmer let u implement the rom file into your memory

Regards

 

[Jayson]

are there any reference designs that show how to add external memory and make it dump its contents to the FPGA upon bootup, etc to create a self-running application?

Secondly, does that mean that you can only run your thing a minimum of 10000 times sucessfully because thats how many program cycles are quaranteed by the device spec?

Do you program the external memory using iMpact? How do you program the external memory, and how later does the FPGA know to download the code from it?

- Jayson

 

[incognito]

>are there any reference designs that show how to add external memory >and make it dump its contents to the FPGA upon bootup, etc to create a >self-running application?

dunno, prolly look in the familly datasheet

>Secondly, does that mean that you can only run your thing a minimum >of 10000 times sucessfully because thats how many program cycles are >quaranteed by the device spec?
indeed, it is

>Do you program the external memory using iMpact?
ya with impact, in the gui => Generate PROM file

> How do you program the external memory
with a memory programmer depend the prom u gonna use u can find some 5$ programmer... serial protocols ain't that hard

>and how later does theFPGA know to download the code from it?

again look at the datasheet FPGA got some MODE pins

Regards

 

[my_garden]

Hi Jayson
Maybe you can use one smallest CPLD with one cheap Flash to do the program work.
When power on, the Cpld can do the work just like the expensive PROM.

 

[phoenixfeng]

hi
you can use the ise quick start!