i just compiled and it pass, but will it work?
| Code VHDL - [expand] |
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| entity MUX is
Port (
EN : in STD_LOGIC;
A_IN : in STD_LOGIC;
B_IN : in STD_LOGIC;
C_IN : in STD_LOGIC;
D_IN : in STD_LOGIC;
RES : in STD_LOGIC;
MUX_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end MUX;
architecture Behavioral of MUX is
signal INPUT_PROCESS : std_logic_vector(3 downto 0);
begin
process (EN, RES)
begin
if RES ='0' then
INPUT_PROCESS <= (others => '0');
elsif EN ='1' then
INPUT_PROCESS(0) <= D_IN;
INPUT_PROCESS(1) <= C_IN;
INPUT_PROCESS(2) <= B_IN;
INPUT_PROCESS(3) <= A_IN;
end if;
end process;
MUX_OUT <= INPUT_PROCESS; |
end Behavioral;
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