Help with VHDL code for multiplier

[tabascorez]

Hello

Can somebody help me with the vhdl code in the attachment. When I elaborate it on design vision, I get the error below. Does anyone know why so and can help out? Thanks

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity mult is
  generic (
    N    : natural :=56
  );
  port (
    a_in : in  std_logic_vector(N-1 downto 0);
    b_in : in  std_logic_vector(N-1 downto 0);
    y    : out std_logic_vector(2*N-1 downto 0)
   );
end mult;
 
architecture structural of mult is
  type ab_type is
    array(N-1 downto 0) of std_logic_vector(N-1 downto 0);
  type c_type is
    array(N-1 downto 0) of std_logic_vector(N downto 1);
  type s_type is
    array(N-1 downto 0) of std_logic_vector(N-1 downto 0);
  --
  signal ab      : ab_type; 
  signal c       : c_type;
  signal s       : s_type;
  signal d       : std_logic_vector(N+1 downto 1);
  signal an      : std_logic;
  signal bn      : std_logic;
  signal sNm1Nm1 : std_logic;
  --
  component fa
    port(
      ain  : in  std_logic;
      bin  : in  std_logic;
      cin  : in  std_logic;
      sout : out std_logic;
      cout : out std_logic
    );
  end component;
begin
 
  -- bit product
  gen_ab_i:
  for i in 0 to N-1 generate
    gen_ab_j: for j in 0 to N-1 generate
      g_abn_leftcol: if (i = N-1) and (j /= N-1) generate
        ab(i)(j) <= a_in(i) and not (b_in(j));
      end generate g_abn_leftcol;
      g_anb_btmrow: if (i /= N-1) and (j = N-1) generate
        ab(i)(j) <= not(a_in(i)) and b_in(j);
      end generate g_anb_btmrow;
      g_ab_btmleft: if (i = N-1) and (j = N-1) generate
        ab(i)(j) <= a_in(i) and b_in(j);
      end generate g_ab_btmleft;
      g_ab_middle: if (i /= N-1) and (j /= N-1) generate
        ab(i)(j) <= a_in(i) and b_in(j);
      end generate g_ab_middle;
    end generate gen_ab_j;
  end generate gen_ab_i;
  
  -- top row
  gen_c_top_row:
  for i in 0 to N-2 generate
    c(i)(1) <= '0';
  end generate gen_c_top_row;
  gen_s_top_row:
  for i in 0 to N-1 generate
    s(i)(0) <= ab(i)(0);
  end generate gen_s_top_row;
   
  -- leftmost column
  gen_s_left_col:
  for j in 1 to N-1 generate
    s(N-1)(j) <= ab(N-1)(j);
  end generate gen_s_left_col;
     
  -- full-adder matrix
  gen_fa_i:
  for i in 0 to N-2 generate
    gen_fa_j:
    for j in 1 to N-1 generate
      u_fa : fa 
        port map (
          ain  => s(i+1)(j-1),
          bin  => ab(i)(j),
          cin  => c(i)(j),
          sout => s(i)(j),
          cout => c(i)(j+1)
        );
    end generate gen_fa_j;
  end generate gen_fa_i;
           
  -- special (N-1,N-1) fa
  an <= not(a_in(N-1));
  bn <= not(b_in(N-1));
  u_fa_nm1sq : fa 
    port map (
      ain  => an,
      bin  => ab(N-1)(N-1),
      cin  => bn,
      sout => sNm1Nm1,
      cout => c(N-1)(N)
    );
      
  -- final stage adder
  gen_fsa: 
  for i in 0 to N generate
    gen_fsa_0: 
    if i = 0 generate
      u_fa_fsa_0 : fa 
        port map (
          ain  => s(i)(N-1),
          bin  => b_in(N-1),
          cin  => a_in(N-1),
          sout => y(i+N-1),
          cout => d(1)
        );
    end generate gen_fsa_0;
    gen_fsa_mid: 
    if i > 0 and i < N-1 generate
      u_fa_fsa_mid : fa 
        port map (
          ain  => s(i)(N-1),
          bin  => d(i),
          cin  => c(i-1)(N),
          sout => y(i+N-1),
          cout => d(i+1)
        );
    end generate gen_fsa_mid;
    gen_fsa_n : if i = N-1 generate
      u_fa_fsa_n : fa 
        port map (
          ain  => sNm1Nm1,
          bin  => d(i),
          cin  => c(i-1)(N),
          sout => y(i+N-1),
          cout => d(i+1)
        );
    end generate gen_fsa_n;
    gen_fsa_np1 : if i = N generate
      u_fa_fsa_np1 : fa 
        port map (
          ain  => '1',
          bin  => d(i),
          cin  => c(i-1)(N),
          sout => y(i+N-1),
          cout => d(i+1)
        );
    end generate gen_fsa_np1;
  end generate gen_fsa;
               
  -- bottom row and output (lower half)
  gen_out:
  for j in 0 to N-2 generate
    y(j) <= s(0)(j);
  end generate gen_out;
   
end structural;

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[verylsi]

M not getting the error with ur code, btw, which synthesis tool are you using ?

 

[ads-ee]

No issue after I added a fa.vhd file to the design. You do know this is a very large combinational circuit. Using Vivado it ends up with >60 levels of logic (LUTs) from a_in to y. Of course I didn't add any constraints to try and improve the timing.
e.g.


Regards

 

[tabascorez]

M not getting the error with ur code, btw, which synthesis tool are you using ?

Use Synopsis