help with verilog code

[behzadmsl]

hi,i'm completely new to verilog, what is the meaning of following code

`define LGIW 6
`define LOG2ICACHESIZE (LGIW+3)
parameter icachesize = 2**LOG2ICACHESIZE;

input [icachesize-1:0] mem_wrdata;


what will the value of "mem_wrdata "be??

tanx in advnace

 

[rberek]

You don't have anything named mem_icache in the code that you show...

 

[behzadmsl]

yes u r right friend,i had typed wrong,i should had written "mem_wrdata" instead of "mem_icache", i edited my previous post and corrected it,could u please chek it again!!

also i have another problem,what does this code mean : " output [0:0] mem_odt ; " ??? isn't it reasonable if we had defined it this way: " output mem_odt; " ????

 

[rberek]

mem_wrdata will be an input port 512 bits wide.

r.b.

 

[behzadmsl]

what is the benefit of having a 512bit wide input port in a module which gets its value from a 32bits wide output port of another module??

 

[rberek]

There is no benefit at all.

If it is truly a 32-bit port tied to a 512-bit port, at very least synthesis will flag this as a warning and attempt optimize away the extra 480 bits.

The 32-bit port could be concatenated with 480 other bits to make the connection. Or, more likely, the parameter icahesize would be redefined somewhere else in the code to be 5. When using a parameter to define a port width, there is usually a default value defined in case the user forgets to set the parameter.

r.b.

 

[behzadmsl]

i have written parts of my code ,processor is my top level module,and another thing to add is that "mem_dcache_wb" module has "altsyncram" megafunction which its input 'a' has been assigned with "bus_writedata"...

i wanna know why an 512 bits wide port has been connected to a 128 bits wide port ??

module processor (clk,resetn);
input clk,resetn;
`define LGDW 6
`define LOG2DCACHEWIDTHBITS (`LGDW+3)
parameter DCACHEWIDTHBITS=2**LOG2DCACHEWIDTHBITS;
wire [DCACHEWIDTHBITS-1:0] dcpu_writedata_line;
core c1(.clk(clk),
.resetn(resetn),
.dbus_writedata_line(dcpu_writedata_line);
always @ (posedge clk)
dcache_writedata<=dcpu_writedata_line;
mem_dcache_wb d1 (.clk(clk),
.resetn(resetn),
.bus_writedata(dcache_writedata));
/***************************
module core (
clk,
resetn,dbus_writedata_line);
input clk,resetn;
output dbus_writedata_line;
`define LGDW 6
`define LOG2DCACHEWIDTHBITS (`LGDW+3)
parameter DCACHEWIDTHBITS=2**LOG2DCACHEWIDTHBITS;
output [DCACHEWIDTHBITS-1:0] dbus_writedata_line
endmodule
//***********************************************************
module mem_dcache_wb(
clk,resetn,bus_writedata);

parameter LOG2CACHEDEPTH=6;
parameter LOG2CACHELINESIZE=7
parameter CACHELINESIZE=2**LOG2CACHELINESIZE;

input clk,resetn;
input [CACHELINESIZE-1:0] bus_writedata;

altsyncram data
(
.clock0 (bus_clk),
.clocken0 (bus_en),
.wren_a (bus_wren),
.byteena_a (bus_byteen_t),
.data_a (bus_writedata_t),
.address_a (bus_address[`OFFSETRANGE]),
.q_a (cache_dataout),
.clock1 (mem_clk),
.wren_b (t_mem_fillwe),
.data_b (mem_filldata),
.address_b (mem_filladdr[`OFFSETRANGE]),
.q_b (mem_lineout)
);

defparam
data.operation_mode = "BIDIR_DUAL_PORT",
data.width_a = CACHELINESIZE, //32-bit specific
data.widthad_a = LOG2CACHEDEPTH,
data.width_byteena_a = CACHELINESIZE/8,
data.width_b = CACHELINESIZE,
data.widthad_b = LOG2CACHEDEPTH,
data.outdata_reg_a = "UNREGISTERED",
data.outdata_reg_b = "UNREGISTERED",
data.rdcontrol_reg_b = "CLOCK1",
data.address_reg_b = "CLOCK1";


endmodule