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A flip flop will divide by 2, so you will not get the same output as the input.
You could try some simple CMOS gates, like a hex inverter. Every 2 gates you add in series will give you two gate delays, and the same output as the input. If you need more time delay, you can use a series R/shunt C to form a lowpass filter inbetween two gates that will slow down the waveform.
There are actual digital "delay line" chips available with a fixed time delay.
the first thing i'm thinkin of is a shift register. You put n flip flops with Q connected with D, all with the same clock. The datum will be available at the end of the cascade after n*Tck seconds. However, if u have fast clock, the number of flip flops will rapidly increase. Maybe there are better solutions.
If you have only D-FFs, build so long chain of they as you have an (every D-ff divide by 2) divided F-Clock to Fclk=1/5sec!
Do you have "so much" FFs in your system?
K.
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