Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

help with pipelining counters

Status
Not open for further replies.

kcinimod

Member level 3
Joined
Dec 19, 2011
Messages
63
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,714
hi all, would it be more efficient to pipeline 4 counters, one for the ones, one for the tens, one for the hundreds and one for the thousands instead of having just one counter count from 1 to 10000 ?
 

Hello kcinimod,
What ever you got an idea is good for design like a digital clock,
Example if we use a one counter we have to say time is 70 sec it is some what not good
if we use two counters one for sec and one for min then we can say 1 min 10 sec its good.
Both are good only based on our requirement we have to choose.
comes to our problem to count 10000 ya right now see what is h/w required 5 counters 5 comparators and reset mux.
buts to count 10000 1 counter and 1 comparator is enough

what ever the application based we have to select the type as pipeline or normal counter.

In real time less hardware is preferable because less hardware leads to less chip size.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top