Help with my rom issue

[cristiano7]

HI,

i want to save in a ROM those vectors:
vector1(0 to 3)<=x"0000";
vector2(0 to 3)<=x"0001";
vector3(0 to 3)<=x"0010";
And each time i want to take one of them in order to xor it with another signal( MEP(0 to 3) ) which is coming from another component.
The problem is that during synthesis it says that
FF/Latch <DATA_0> has a constant value of 0 in block <ROM>. This FF/Latch will be trimmed during the optimization process.

FF/Latch <DATA_1> has a constant value of 0 in block <ROM>. This FF/Latch will be trimmed during the optimization process.


I believe that this happens because the first two bits are the same for those vectors. And it says that they will be trimmed! If the will be trimmed then i will lose them , right? So on the FPGA i will lose those bits, and then how can i do the xor with the signal MEP? I need those trimmed signals!

 

[TrickyDicky]

but according to your (very limited) code, bits 0 and 1 are always 0, hence why they are trimmed. They have no function. any XOR with them will just give the other bit.