Help with IO logic pad

[papanatas]

Dear forum members,

I'm currently studying an old early 90s IC and curious about the structure of the data pad below. I know the right most line is an input but I have no idea what the other two connections are for?

Any ideas/comments appreciated.

 

[gag2000]

Hi,

Most likely, other nets are vdd and gnd, used for polarising input protection (looks like reverse PN diodes : one between gnd and input, the other one between input and vdd).

Regards,
RG

 

[erikl]

I know the right most line is an input but I have no idea what the other two connections are for?

I think it's an IOpad: the middle one is the tristate control, the left one the output from core to the pad driver.

 

[papanatas]

Thanks both for the feedback. I analyzed this further and I think they are the HIGH and LOW driver signals.

When both are LOW the gate seems to output HIGH, and when both go HIGH the gate outputs a LOW. In addition, when the signals opposite each other the gate seems to go into input mode rather than output.

Makes sense?

 

[erikl]

When both are LOW the gate seems to output HIGH, and when both go HIGH the gate outputs a LOW. In addition, when the signals opposite each other the gate seems to go into input mode rather than output.

Makes sense?

Not really, IMHO: A tristate input should enable/disable (either high or low active) the output. If disabled, the output should be tristate, but it is possible that it includes a pull-up or pull-down resistor. So your above measured result is probably explainable.

 

[dick_freebird]

I have seen I/O pad cells which divorce the output taper's
control signals from the pad region (using H and L control
signals derived from data and tristate ones), placing an
"ioctrl" cell in the logic core for this. This seems consistent
with the OP's analysis of signal outcomes. I have also seen
data & tristate as direct inputs, and an ESD-protected pad
feedback (input) ought to be part of the core-routed signal
set if it's truly a general purpose I/O.