On a real circuit, values can only be '1' or '0'. In VHDL, they will default to 'UUU' (uninitialised). Any good synthesisor should take the power up value from the asynchronous reset state, so on your FPGA the counter should start from "100000.." when it powers on. If you never reset it, and it is always counting, it will overflow back to "00000".
You have only posted a small snippet of your code. Reset conditions are perfectly normal in VHDL, and there is usually no need to reset logic in hardware. Its usually best to asert the async reset at the start of a testbench.