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help with behavioral cache verilog coding

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deepa1206

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help with verilog coding

Need some help with Verilog coding

Hi

I am trying to code a behavioral cache design in Verilog, since I am familiar with C , I end up coding in the same style and i am stuck:

This is what I am trying to do:

My cache has 4 WAYS, I am checking the TAG bits and the VALID bits in a particular CACHE LINE in in all the 4 WAYS( which I am checking in a for loop). and I am trying to find out which WAY has a HIT.(when TAG matches and VALID=`VALID), can anyone tell me what is wrong with the following code? I get an error in ModelSIM- "Illegal reference to net HitWay "
PLease help.

module HitSignalGenerator(TagSelectInput,LineSelectInput,RW,HitWay,RW_HM);

input [`NUM_TAG_BITS-1:0] TagSelectInput;
input [`LINE_SELECT-1:0] LineSelectInput;
input RW;
output [`WAY_SELECT-1:0] HitWay;
output [`RW_HM_SELECT-1:0] RW_HM;


reg [`WAY_SELECT-1:0] i;

always@(TagSelectInput,LineSelectInput,RW) begin

for(i=0;i<`NUM_OF_WAYS;i=i+1) begin
if( (L2_Cache.TagRAM[LineSelectInput] == TagSelectInput) && (L2_Cache.ValidRAM[LineSelectInput] == `VALID) ) begin
HitWay = i;
end
end

end
endmodule;
 

Re: help with verilog coding

Hi,

HitWay is inside always has to be declared as a reg.

add this line before always and it should compile fine.
reg [`WAY_SELECT -1:0] HitWay;

By the way endmodule should not have semicolon either.
 

Re: help with verilog coding

Thank you kochirojave.


Is it possible to write the above code using only wires? If yes, how can I replace the for /if statements?

Also how does the register "i" in the code get synthesized? Will it be a counter? If yes, when does it get incremented since I dont have a clock?

Thanks
 

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