wood_girl
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Hola,
Ok, this is what I measured:
======================================
Rset=6k8, Rload = 200, Vcc = 3,3V, Fmclk=72MHz:
-----------------------------------------------------------------
1) Fout=10Hz => Vp-p=570mV (from 40mV to 610mV)
2) Fout=10kHz => Vp-p=370mV (from 140mV to 510mV)
3) Fout=1MHz => Vp-p=340mV (from 150mV to 490mV)
4) Fout=10MHz => Vp-p=260mV (from 200mV to 460mV)
======================================
Fmclk=46,6MHz:
-----------------------------------------------------------------
1) Fout=10MHz => Vp-p=260mV (from 200mV to 460mV)
======================================
So, my results are similar to those that you got on the pictures you attached. I don't quite understand the diagrams that you received from Analog Devices.
So, regarding your disappointment about DDS, I think that you can not do much better than this. You can go to the configuration page of AD9834 on Analog.com at address
**broken link removed**
and try with different values. You can try to lower the Rset to achive higher output, but the maximum of Vout=Iout*Rload can not exceed 0,8V.
This is just it, not only for this DDS but for the others, too. Unless they have some amplifier built-in. Usually, DDS is used in some PLL circuitry, so output signal is not directly from DDS.
Or, maybe we are both doing something wrong.
Another thing about DDS, in general. I tested 2 DDS chips that work synchronously and I wanted to generate two signals with the same frequency of F1=F2=Fmclk/2, and to control the phase shift beetwen those two signals. In this case that can not be done, because of the "Fmclk/2 thing". I wanted to sweep the phase difference, but the only thing is that the signal, which phase is changed, is decreasing in amplitude (for the phase2 from 0 to 180) but still in phase with first signal, and then they are in counterphase (for the phase2 from 180 to 360).
Crazy thing.
Ok, now I'll tell you what else I did, but I do not recommend this to anyone.
Since I was driving the Fmclk input of DDS with one signal generator, I could increase the Fmclk. So I tried with Fmclk = 100MHz, and it worked. Then I tried with Fmclk = 150MHz, and it worked. Then I tried with Fmclk = 250MHz, and it worked. It worked up to Fmclk = 400MHz, and then I had to increase power level of clock signal. Funny thing is that DDS chip was still pretty cool (of course with increased consumption).
So, you can eventually increase Fmclk beyond 75MHz and thus increase amplitude on 10MHz (but I still don't recommend this).
Salud
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