help with a MAX2769B receiver IC

[JHEnt]

I have been having trouble getting a Maxim MAX2769B chip to work on a protoboard. I'm hoping someone here has worked with one of these before. Basically I have tried mounting several to proto-advantage boards. The latest one I took extra care to mount all mount all of the decoupling, AC coupling, DC blocking capacitors and the PLL CRC filter onto the board with SMD components. It seemed although I had no I/Q outputs that the chip was otherwise functioning. It was outputting 3.2 volt on the ANT-BIAS pin and for a while I had a 2.5 volt output on the PLL lock indicator pin. I could also pick up millivolt levels on the RF in out and external XTAL leads. I have laid out the board along the "typical application circuit" in Maxim's spec sheet. Is there something non-obvious I'm doing wrong? I have read very few cases where this chip was used in projects online except when mounted on the evaluation kit direct from Maxim. I have read several blogs ect where a problem sounding much like mine is reported.

I am trying to use LNA1 input. I'm powering it with 3.3volt. I am using an Abracon 16.38676MHz TXCO with a 10nF coupling capacitor to the external reference pin. I'm pulling up the IDLE, SHTDWN pins and grounding the PGM so as to use a preconfigured state by pulling the SDATA high and the SCLK and CS pins low.

I have tried mounting these myself. I certainly wouldn't exclude the posibility of solder shorted contacts under the chip but then why should it seem to be functioning and then just stop.

Is there anyone who has made one of these chips work?

 

[clive1]

Used the original MAX2769 on a couple of receiver boards, large ground pad is critical, along with multiple supply pins. I programmed via SPI pins, not strapping. Didn't use the dev board, built a circuit very similar to the reference, and integrated it into our design.

Confirm you have a base band clock coming out of CLKOUT, check the DC offset and peak-to-peak voltage of the clock at XTAL

My biggest issue with the part was it was tuned for 4.092 MHz operation for the down converted signal, and it really didn't like being set in the negative frequency domain. I was using it to replace 2740/2741 parts. The secondary issue seem to be that reprogramming the settings blanked the clock briefly.

 

[JHEnt]

I appreciate the reply. My Proto-Advantage board stuck into a breadboard obviously do not have a good ground plane. That in itself could be a major factor in my troubles.

As of right now it appears I have a decent CLKOUT signal at least according to and LED I have tied to that input of the FPGA logic. I also appear to have some kind of I sign /mag data comming in. I have a logic high of 2.5volt on the PLL lock detect. The last thing I changed was the pull up resistor I was using on the serial DATA line. I had a 100K and changed it down to a 100ohm resistor. I found previously that if direct tie those serial lines to 3.3v it will pull enough current to heat up 3.3v regulator untill it shuts down.
So I may have data comming in or I may just have static at this point.

Maxim has been very little help on a few questions. First I asked them about the sampling rate. Thier only response was that it was nealy 5Msps. I am assuming that the samples are encoded with the reference clk?? But is it sampled at the downconverted IF 4.092MHz rate? Is it safe to assume that the samples must be read at either posedge or negedge of the CLKOUT signal?

I dont have access to an oscilliscope. I should just buy one. I'm thinking of just buying the evaluation kit so I can get my FPGA logic running first then come back to trying to make my own RF receiver board.

 

[clive1]

Well, my understanding of the 2769 is the sample rate is the reference clock (20 MHz in my case, ~16.387 MHz in yours), and that you can program the PLL to get the desired IF, and configure the filtering around the IF. I ended up writing a fitter app to generate register setting (based on filter equations from Maxim), but the default should be fine.

I got little useful help from Maxim and was unable to get a clear model for the internal functionality of the design, what I did discover was the IF needed to be in the +4 .. 5 MHz region, and I really wanted -4.58 MHz (ie 1575.420 - 1580), which mixed with 5 MHz gets me to 420 KHz.

The pad under the part is the ground, if your regulator is overloading, I'd suspect some short.

 

[JHEnt]

Well I broke down and just bought the evaluation kit and a scope. I have it set to mix 1571.328 which should give me a +4.092 IF. I set my numerical sine generator for a center of 4.092. My NCO sine wave checks out as approx 4.09MHz. However in looking at the incomming data from the Maxim chip there appears to be a much slower IF. My scope will not give freq reading for the modulated data from the 2769 chip but it is much slower than 4 MHz. Seems like it is around 1MHz or so. its made testing my FPGA logic a bit frustrating. Did you have any problems like this with your project?